Merge "cnss2: Add debug dump for Wlan FW PBL and SBL"
This commit is contained in:
commit
ab42af6e3d
2 changed files with 80 additions and 21 deletions
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@ -74,9 +74,6 @@ static DEFINE_SPINLOCK(time_sync_lock);
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#define LINK_TRAINING_RETRY_MAX_TIMES 3
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#define CNSS_DEBUG_DUMP_SRAM_START 0x1403D58
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#define CNSS_DEBUG_DUMP_SRAM_SIZE 10
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#define HANG_DATA_LENGTH 384
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#define HST_HANG_DATA_OFFSET ((3 * 1024 * 1024) - HANG_DATA_LENGTH)
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#define HSP_HANG_DATA_OFFSET ((2 * 1024 * 1024) - HANG_DATA_LENGTH)
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@ -1684,6 +1681,70 @@ static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv)
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}
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#endif
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/**
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* cnss_pci_dump_bl_sram_mem - Dump WLAN FW bootloader debug log
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* @pci_priv: PCI device private data structure of cnss platform driver
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*
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* Dump Primary and secondary bootloader debug log data. For SBL check the
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* log struct address and size for validity.
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*
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* Supported only on QCA6490
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*
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* Return: None
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*/
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static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
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{
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int i;
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u32 mem_addr, val, pbl_stage, sbl_log_start, sbl_log_size;
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struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
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if (plat_priv->device_id != QCA6490_DEVICE_ID)
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return;
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if (cnss_pci_check_link_status(pci_priv))
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return;
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cnss_pci_reg_read(pci_priv, QCA6490_TCSR_PBL_LOGGING_REG, &pbl_stage);
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cnss_pci_reg_read(pci_priv, QCA6490_PCIE_BHI_ERRDBG2_REG,
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&sbl_log_start);
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cnss_pci_reg_read(pci_priv, QCA6490_PCIE_BHI_ERRDBG3_REG,
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&sbl_log_size);
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cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: 0x%08x 0x%08x",
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pbl_stage, sbl_log_start, sbl_log_size);
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cnss_pr_dbg("Dumping PBL log data");
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/* cnss_pci_reg_read provides 32bit register values */
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for (i = 0; i < QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE; i += sizeof(val)) {
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mem_addr = QCA6490_DEBUG_PBL_LOG_SRAM_START + i;
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if (cnss_pci_reg_read(pci_priv, mem_addr, &val))
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break;
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cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
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}
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if (plat_priv->device_version.major_version == FW_V2_NUMBER) {
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if (sbl_log_start > QCA6490_V2_SBL_DATA_START &&
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(sbl_log_start + sbl_log_size) < QCA6490_V2_SBL_DATA_END)
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goto dump_sbl_log;
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} else {
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if (sbl_log_start > QCA6490_V1_SBL_DATA_START &&
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(sbl_log_start + sbl_log_size) < QCA6490_V1_SBL_DATA_END)
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goto dump_sbl_log;
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}
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cnss_pr_err("Invalid SBL log data");
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return;
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dump_sbl_log:
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cnss_pr_dbg("Dumping SBL log data");
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sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
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QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
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for (i = 0; i < sbl_log_size; i += sizeof(val)) {
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mem_addr = sbl_log_start + i;
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if (cnss_pci_reg_read(pci_priv, mem_addr, &val))
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break;
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cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
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}
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}
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static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv)
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{
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int ret = 0;
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@ -2137,8 +2198,10 @@ int cnss_wlan_register_driver(struct cnss_wlan_driver *driver_ops)
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msecs_to_jiffies(timeout) << 2);
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if (!ret) {
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cnss_pr_err("Timeout waiting for calibration to complete\n");
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if (!test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state))
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if (!test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
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cnss_pci_dump_bl_sram_mem(pci_priv);
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CNSS_ASSERT(0);
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}
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cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
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if (!cal_info)
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@ -3810,21 +3873,6 @@ static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv,
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}
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}
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static void cnss_pci_dump_sram_mem(struct cnss_pci_data *pci_priv)
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{
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int i;
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u32 mem_addr, val;
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if (cnss_pci_check_link_status(pci_priv))
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return;
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for (i = 0; i < CNSS_DEBUG_DUMP_SRAM_SIZE; i++) {
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mem_addr = CNSS_DEBUG_DUMP_SRAM_START + i * 4;
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if (cnss_pci_reg_read(pci_priv, mem_addr, &val))
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return;
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cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);
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}
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}
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static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)
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{
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cnss_pr_dbg("Start to dump debug registers\n");
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@ -3857,7 +3905,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv)
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cnss_auto_resume(&pci_priv->pci_dev->dev);
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cnss_pci_dump_misc_reg(pci_priv);
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cnss_pci_dump_shadow_reg(pci_priv);
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cnss_pci_dump_sram_mem(pci_priv);
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cnss_pci_dump_bl_sram_mem(pci_priv);
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ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);
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if (ret) {
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@ -4008,7 +4056,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
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cnss_pci_dump_misc_reg(pci_priv);
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cnss_pci_dump_qdss_reg(pci_priv);
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cnss_pci_dump_sram_mem(pci_priv);
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cnss_pci_dump_bl_sram_mem(pci_priv);
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ret = mhi_download_rddm_img(pci_priv->mhi_ctrl, in_panic);
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if (ret) {
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@ -267,4 +267,15 @@
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#define QCA6390_SYSPM_DBG_BUS_SEL_REG 0x1F82008
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#define QCA6390_SYSPM_WCSSAON_SR_STATUS 0x1F8200C
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#define QCA6490_DEBUG_PBL_LOG_SRAM_START 0x1403D58
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#define QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40
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#define QCA6490_V1_SBL_DATA_START 0x143b000
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#define QCA6490_V1_SBL_DATA_END (0x143b000 + 0x00011000)
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#define QCA6490_V2_SBL_DATA_START 0x1435000
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#define QCA6490_V2_SBL_DATA_END (0x1435000 + 0x00011000)
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#define QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48
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#define QCA6490_TCSR_PBL_LOGGING_REG 0x01B000F8
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#define QCA6490_PCIE_BHI_ERRDBG2_REG 0x01E0E238
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#define QCA6490_PCIE_BHI_ERRDBG3_REG 0x01E0E23C
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#endif
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