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ARM: S3C64XX: 2nd Change to using s3c_gpio_cfgall_range()

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This patch changes the code setting range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgpin_range().
NOTE: This is for missed things from the previous patch.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim 2010-10-01 20:47:21 +09:00
parent 861004657e
commit aef698a72f
2 changed files with 7 additions and 20 deletions
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10
arch/arm/mach-s3c64xx/setup-ide.c
View file

@ -21,7 +21,6 @@
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
u32 gpio = 0;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
@ -32,15 +31,12 @@ void s3c64xx_ide_setup_gpio(void)
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}

17
arch/arm/mach-s3c64xx/setup-keypad.c
View file

@ -15,20 +15,11 @@
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
unsigned int gpio;
unsigned int end;
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
end = S3C64XX_GPK(8 + rows);
for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_cfgall_range(S3C64XX_GPK(8), 8 + rows,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
end = S3C64XX_GPL(0 + cols);
for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_cfgall_range(S3C64XX_GPL(0), cols,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
}