[ARM] omap: eliminate unnecessary conditionals in omap2_clk_wait_ready
Rather than employing run-time tests in omap2_clk_wait_ready() to decide whether we need to wait for the clock to become ready, we can set the .ops appropriately. This change deals with the OMAP24xx and OMAP34xx conditionals only. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
parent
b36ee72420
commit
bc51da4ee4
4 changed files with 35 additions and 32 deletions
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@ -237,23 +237,6 @@ static void omap2_clk_wait_ready(struct clk *clk)
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else
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return;
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/* REVISIT: What are the appropriate exclusions for 34XX? */
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/* No check for DSS or cam clocks */
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if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
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if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
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clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
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clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
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return;
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}
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/* REVISIT: What are the appropriate exclusions for 34XX? */
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/* OMAP3: ignore DSS-mod clocks */
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if (cpu_is_omap34xx() &&
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(((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
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((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
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clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
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return;
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/* Check if both functional and interface clocks
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* are running. */
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bit = 1 << clk->enable_bit;
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@ -264,7 +247,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
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omap2_wait_clock_ready(st_reg, bit, clk->name);
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}
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static int omap2_dflt_clk_enable_wait(struct clk *clk)
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static int omap2_dflt_clk_enable(struct clk *clk)
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{
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u32 regval32;
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@ -282,11 +265,25 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk)
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__raw_writel(regval32, clk->enable_reg);
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wmb();
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omap2_clk_wait_ready(clk);
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return 0;
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}
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static int omap2_dflt_clk_enable_wait(struct clk *clk)
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{
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int ret;
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if (unlikely(clk->enable_reg == NULL)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0; /* REVISIT: -EINVAL */
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}
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ret = omap2_dflt_clk_enable(clk);
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if (ret == 0)
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omap2_clk_wait_ready(clk);
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return ret;
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}
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static void omap2_dflt_clk_disable(struct clk *clk)
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{
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u32 regval32;
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@ -315,6 +312,11 @@ const struct clkops clkops_omap2_dflt_wait = {
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.disable = omap2_dflt_clk_disable,
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};
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const struct clkops clkops_omap2_dflt = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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};
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/* Enables clock without considering parent dependencies or use count
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* REVISIT: Maybe change this to use clk->enable like on omap1?
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*/
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@ -52,6 +52,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
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void omap2_clk_prepare_for_reboot(void);
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_omap2_dflt;
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extern u8 cpu_mask;
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@ -1455,7 +1455,7 @@ static const struct clksel dss1_fck_clksel[] = {
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static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
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.name = "dss_ick",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &l4_ck, /* really both l3 and l4 */
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.clkdm_name = "dss_clkdm",
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@ -1466,7 +1466,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
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static struct clk dss1_fck = {
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.name = "dss1_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &core_ck, /* Core or sys */
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
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DELAYED_APP,
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@ -1500,7 +1500,7 @@ static const struct clksel dss2_fck_clksel[] = {
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static struct clk dss2_fck = { /* Alt clk used in power management */
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.name = "dss2_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
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DELAYED_APP,
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@ -2206,7 +2206,7 @@ static struct clk icr_ick = {
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static struct clk cam_ick = {
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.name = "cam_ick",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &l4_ck,
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.clkdm_name = "core_l4_clkdm",
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@ -2222,7 +2222,7 @@ static struct clk cam_ick = {
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*/
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static struct clk cam_fck = {
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.name = "cam_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &func_96m_ck,
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.clkdm_name = "core_l3_clkdm",
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@ -1652,7 +1652,7 @@ static const struct clksel ssi_ssr_clksel[] = {
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static struct clk ssi_ssr_fck = {
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.name = "ssi_ssr_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.init = &omap2_init_clksel_parent,
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP3430_EN_SSI_SHIFT,
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@ -2064,7 +2064,7 @@ static struct clk ssi_l4_ick = {
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static struct clk ssi_ick = {
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.name = "ssi_ick",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &ssi_l4_ick,
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP3430_EN_SSI_SHIFT,
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@ -2156,7 +2156,7 @@ static const struct clksel dss1_alwon_fck_clksel[] = {
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static struct clk dss1_alwon_fck = {
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.name = "dss1_alwon_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &dpll4_m4x2_ck,
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.init = &omap2_init_clksel_parent,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
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@ -2171,7 +2171,7 @@ static struct clk dss1_alwon_fck = {
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static struct clk dss_tv_fck = {
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.name = "dss_tv_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &omap_54m_fck,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
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@ -2183,7 +2183,7 @@ static struct clk dss_tv_fck = {
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static struct clk dss_96m_fck = {
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.name = "dss_96m_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &omap_96m_fck,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
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@ -2195,7 +2195,7 @@ static struct clk dss_96m_fck = {
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static struct clk dss2_alwon_fck = {
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.name = "dss2_alwon_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &sys_ck,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
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@ -2208,7 +2208,7 @@ static struct clk dss2_alwon_fck = {
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static struct clk dss_ick = {
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/* Handles both L3 and L4 clocks */
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.name = "dss_ick",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &l4_ick,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
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