Merge commit 'gcl/gcl-next'
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c174aff956
4 changed files with 95 additions and 6 deletions
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@ -59,6 +59,7 @@ Table of Contents
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p) Freescale Synchronous Serial Interface
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p) Freescale Synchronous Serial Interface
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q) USB EHCI controllers
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q) USB EHCI controllers
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r) MDIO on GPIOs
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r) MDIO on GPIOs
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s) SPI busses
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VII - Marvell Discovery mv64[345]6x System Controller chips
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VII - Marvell Discovery mv64[345]6x System Controller chips
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1) The /system-controller node
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1) The /system-controller node
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@ -1883,6 +1884,62 @@ platforms are moved over to use the flattened-device-tree model.
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&qe_pio_c 6>;
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&qe_pio_c 6>;
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};
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};
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s) SPI (Serial Peripheral Interface) busses
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SPI busses can be described with a node for the SPI master device
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and a set of child nodes for each SPI slave on the bus. For this
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discussion, it is assumed that the system's SPI controller is in
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SPI master mode. This binding does not describe SPI controllers
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in slave mode.
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The SPI master node requires the following properties:
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- #address-cells - number of cells required to define a chip select
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address on the SPI bus.
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- #size-cells - should be zero.
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- compatible - name of SPI bus controller following generic names
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recommended practice.
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No other properties are required in the SPI bus node. It is assumed
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that a driver for an SPI bus device will understand that it is an SPI bus.
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However, the binding does not attempt to define the specific method for
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assigning chip select numbers. Since SPI chip select configuration is
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flexible and non-standardized, it is left out of this binding with the
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assumption that board specific platform code will be used to manage
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chip selects. Individual drivers can define additional properties to
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support describing the chip select layout.
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SPI slave nodes must be children of the SPI master node and can
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contain the following properties.
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- reg - (required) chip select address of device.
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- compatible - (required) name of SPI device following generic names
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recommended practice
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- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
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- spi-cpol - (optional) Empty property indicating device requires
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inverse clock polarity (CPOL) mode
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- spi-cpha - (optional) Empty property indicating device requires
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shifted clock phase (CPHA) mode
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SPI example for an MPC5200 SPI bus:
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spi@f00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995m";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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codec@1 {
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compatible = "ti,tlv320aic26";
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spi-max-frequency = <100000>;
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reg = <1>;
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};
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};
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VII - Marvell Discovery mv64[345]6x System Controller chips
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VII - Marvell Discovery mv64[345]6x System Controller chips
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===========================================================
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===========================================================
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@ -1,7 +1,6 @@
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config PPC_MPC52xx
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config PPC_MPC52xx
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bool "52xx-based boards"
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bool "52xx-based boards"
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depends on PPC_MULTIPLATFORM && PPC32
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depends on PPC_MULTIPLATFORM && PPC32
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select FSL_SOC
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select PPC_CLOCK
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select PPC_CLOCK
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select PPC_PCI_CHOICE
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select PPC_PCI_CHOICE
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@ -48,6 +47,7 @@ config PPC_MPC5200_BUGFIX
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config PPC_MPC5200_GPIO
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config PPC_MPC5200_GPIO
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bool "MPC5200 GPIO support"
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bool "MPC5200 GPIO support"
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depends on PPC_MPC52xx
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depends on PPC_MPC52xx
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select GENERIC_GPIO
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select HAVE_GPIO_LIB
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select HAVE_GPIO_LIB
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help
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help
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Enable gpiolib support for mpc5200 based boards
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Enable gpiolib support for mpc5200 based boards
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@ -91,8 +91,6 @@ void of_register_i2c_devices(struct i2c_adapter *adap,
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}
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}
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info.irq = irq_of_parse_and_map(node, 0);
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info.irq = irq_of_parse_and_map(node, 0);
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if (info.irq == NO_IRQ)
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info.irq = -1;
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if (of_find_i2c_driver(node, &info) < 0) {
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if (of_find_i2c_driver(node, &info) < 0) {
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irq_dispose_mapping(info.irq);
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irq_dispose_mapping(info.irq);
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@ -60,10 +60,12 @@
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#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
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#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
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#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
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#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
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/* PSC interrupt mask bits */
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/* PSC interrupt status/mask bits */
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#define MPC52xx_PSC_IMR_TXRDY 0x0100
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#define MPC52xx_PSC_IMR_TXRDY 0x0100
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#define MPC52xx_PSC_IMR_RXRDY 0x0200
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#define MPC52xx_PSC_IMR_RXRDY 0x0200
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#define MPC52xx_PSC_IMR_DB 0x0400
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#define MPC52xx_PSC_IMR_DB 0x0400
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#define MPC52xx_PSC_IMR_TXEMP 0x0800
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#define MPC52xx_PSC_IMR_ORERR 0x1000
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#define MPC52xx_PSC_IMR_IPC 0x8000
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#define MPC52xx_PSC_IMR_IPC 0x8000
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/* PSC input port change bit */
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/* PSC input port change bit */
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@ -92,6 +94,34 @@
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#define MPC52xx_PSC_RFNUM_MASK 0x01ff
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#define MPC52xx_PSC_RFNUM_MASK 0x01ff
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#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
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#define MPC52xx_PSC_SICR_SHDR (1 << 28)
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#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
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#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
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#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
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#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
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#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
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#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
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#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
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#define MPC52xx_PSC_SICR_I2S (1 << 22)
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#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
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#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
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#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
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#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
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#define MPC52xx_PSC_SICR_ESAI (1 << 17)
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#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
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#define MPC52xx_PSC_SICR_SPI (1 << 15)
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#define MPC52xx_PSC_SICR_MSTR (1 << 14)
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#define MPC52xx_PSC_SICR_CPOL (1 << 13)
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#define MPC52xx_PSC_SICR_CPHA (1 << 12)
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#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
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#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
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/* Structure of the hardware registers */
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/* Structure of the hardware registers */
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struct mpc52xx_psc {
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struct mpc52xx_psc {
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@ -132,8 +162,12 @@ struct mpc52xx_psc {
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u8 reserved5[3];
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u8 reserved5[3];
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u8 ctlr; /* PSC + 0x1c */
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u8 ctlr; /* PSC + 0x1c */
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u8 reserved6[3];
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u8 reserved6[3];
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u16 ccr; /* PSC + 0x20 */
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/* BitClkDiv field of CCR is byte swapped in
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u8 reserved7[14];
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* the hardware for mpc5200/b compatibility */
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u32 ccr; /* PSC + 0x20 */
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u32 ac97_slots; /* PSC + 0x24 */
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u32 ac97_cmd; /* PSC + 0x28 */
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u32 ac97_data; /* PSC + 0x2c */
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u8 ivr; /* PSC + 0x30 */
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u8 ivr; /* PSC + 0x30 */
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u8 reserved8[3];
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u8 reserved8[3];
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u8 ip; /* PSC + 0x34 */
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u8 ip; /* PSC + 0x34 */
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