ixgbe: Refactor transmit map and cleanup routines
This patch implements a partial refactor of the TX map/queue and cleanup routines. It merges the map and queue functionality and as a result improves the transmit performance by avoiding unnecessary reads from memory. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck
Jeff Kirsher
parent
0ebafd8665
commit
d3d0023979
2 changed files with 255 additions and 224 deletions
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@ -96,6 +96,7 @@
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#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
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#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
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#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
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#define IXGBE_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 6)
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#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
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#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
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@ -141,14 +142,14 @@ struct vf_macvlans {
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct ixgbe_tx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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union ixgbe_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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u16 length;
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u16 next_to_watch;
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unsigned int bytecount;
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dma_addr_t dma;
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u32 length;
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u32 tx_flags;
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struct sk_buff *skb;
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u32 bytecount;
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u16 gso_segs;
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u8 mapped_as_page;
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};
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struct ixgbe_rx_buffer {
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@ -385,7 +385,7 @@ static void ixgbe_dump(struct ixgbe_adapter *adapter)
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tx_ring = adapter->tx_ring[n];
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tx_buffer_info =
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&tx_ring->tx_buffer_info[tx_ring->next_to_clean];
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pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
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pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
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n, tx_ring->next_to_use, tx_ring->next_to_clean,
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(u64)tx_buffer_info->dma,
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tx_buffer_info->length,
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@ -424,7 +424,7 @@ static void ixgbe_dump(struct ixgbe_adapter *adapter)
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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u0 = (struct my_u0 *)tx_desc;
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pr_info("T [0x%03X] %016llX %016llX %016llX"
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" %04X %3X %016llX %p", i,
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" %04X %p %016llX %p", i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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(u64)tx_buffer_info->dma,
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@ -643,27 +643,31 @@ static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
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}
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}
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static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
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struct ixgbe_tx_buffer *tx_buffer)
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{
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if (tx_buffer->dma) {
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if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
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dma_unmap_page(ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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else
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dma_unmap_single(ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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}
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tx_buffer->dma = 0;
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}
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void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
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struct ixgbe_tx_buffer *tx_buffer_info)
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{
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if (tx_buffer_info->dma) {
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if (tx_buffer_info->mapped_as_page)
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dma_unmap_page(tx_ring->dev,
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tx_buffer_info->dma,
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tx_buffer_info->length,
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DMA_TO_DEVICE);
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else
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dma_unmap_single(tx_ring->dev,
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tx_buffer_info->dma,
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tx_buffer_info->length,
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DMA_TO_DEVICE);
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tx_buffer_info->dma = 0;
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}
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if (tx_buffer_info->skb) {
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ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
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if (tx_buffer_info->skb)
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dev_kfree_skb_any(tx_buffer_info->skb);
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tx_buffer_info->skb = NULL;
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}
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tx_buffer_info->time_stamp = 0;
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/* tx_buffer_info must be completely set up in the transmit path */
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}
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@ -797,56 +801,72 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
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struct ixgbe_ring *tx_ring)
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{
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struct ixgbe_adapter *adapter = q_vector->adapter;
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union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
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struct ixgbe_tx_buffer *tx_buffer_info;
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struct ixgbe_tx_buffer *tx_buffer;
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union ixgbe_adv_tx_desc *tx_desc;
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unsigned int total_bytes = 0, total_packets = 0;
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u16 i, eop, count = 0;
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u16 i = tx_ring->next_to_clean;
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u16 count;
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i = tx_ring->next_to_clean;
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eop = tx_ring->tx_buffer_info[i].next_to_watch;
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eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
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while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
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(count < q_vector->tx.work_limit)) {
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bool cleaned = false;
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rmb(); /* read buffer_info after eop_desc */
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for ( ; !cleaned; count++) {
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tx_buffer = &tx_ring->tx_buffer_info[i];
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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for (count = 0; count < q_vector->tx.work_limit; count++) {
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union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
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/* if next_to_watch is not set then there is no work pending */
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if (!eop_desc)
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break;
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/* if DD is not set pending work has not been completed */
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if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
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break;
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/* count the packet as being completed */
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tx_ring->tx_stats.completed++;
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/* clear next_to_watch to prevent false hangs */
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tx_buffer->next_to_watch = NULL;
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/* prevent any other reads prior to eop_desc being verified */
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rmb();
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do {
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ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
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tx_desc->wb.status = 0;
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cleaned = (i == eop);
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if (likely(tx_desc == eop_desc)) {
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eop_desc = NULL;
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dev_kfree_skb_any(tx_buffer->skb);
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tx_buffer->skb = NULL;
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total_bytes += tx_buffer->bytecount;
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total_packets += tx_buffer->gso_segs;
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}
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tx_buffer++;
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tx_desc++;
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i++;
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if (i == tx_ring->count)
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if (unlikely(i == tx_ring->count)) {
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i = 0;
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if (cleaned && tx_buffer_info->skb) {
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total_bytes += tx_buffer_info->bytecount;
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total_packets += tx_buffer_info->gso_segs;
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tx_buffer = tx_ring->tx_buffer_info;
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
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}
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ixgbe_unmap_and_free_tx_resource(tx_ring,
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tx_buffer_info);
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}
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tx_ring->tx_stats.completed++;
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eop = tx_ring->tx_buffer_info[i].next_to_watch;
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eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
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} while (eop_desc);
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}
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tx_ring->next_to_clean = i;
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u64_stats_update_begin(&tx_ring->syncp);
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tx_ring->stats.bytes += total_bytes;
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tx_ring->stats.packets += total_packets;
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u64_stats_update_begin(&tx_ring->syncp);
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u64_stats_update_end(&tx_ring->syncp);
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q_vector->tx.total_bytes += total_bytes;
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q_vector->tx.total_packets += total_packets;
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u64_stats_update_end(&tx_ring->syncp);
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if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
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/* schedule immediate reset if we believe we hung */
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struct ixgbe_hw *hw = &adapter->hw;
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
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e_err(drv, "Detected Tx Unit Hang\n"
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" Tx Queue <%d>\n"
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" TDH, TDT <%x>, <%x>\n"
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@ -858,8 +878,8 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
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tx_ring->queue_index,
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IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
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IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
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tx_ring->next_to_use, eop,
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tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
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tx_ring->next_to_use, i,
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tx_ring->tx_buffer_info[i].time_stamp, jiffies);
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netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
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@ -6406,89 +6426,160 @@ static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
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return (skb->ip_summed == CHECKSUM_PARTIAL);
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}
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static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *tx_ring,
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struct sk_buff *skb, u32 tx_flags,
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unsigned int first, const u8 hdr_len)
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static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
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{
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/* set type for advanced descriptor with frame checksum insertion */
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__le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
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IXGBE_ADVTXD_DCMD_IFCS |
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IXGBE_ADVTXD_DCMD_DEXT);
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/* set HW vlan bit if vlan is present */
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if (tx_flags & IXGBE_TX_FLAGS_VLAN)
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cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
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/* set segmentation enable bits for TSO/FSO */
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#ifdef IXGBE_FCOE
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if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
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#else
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if (tx_flags & IXGBE_TX_FLAGS_TSO)
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#endif
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cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
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return cmd_type;
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}
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static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
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{
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__le32 olinfo_status =
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cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
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if (tx_flags & IXGBE_TX_FLAGS_TSO) {
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olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
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(1 << IXGBE_ADVTXD_IDX_SHIFT));
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/* enble IPv4 checksum for TSO */
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if (tx_flags & IXGBE_TX_FLAGS_IPV4)
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olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
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}
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/* enable L4 checksum for TSO and TX checksum offload */
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if (tx_flags & IXGBE_TX_FLAGS_CSUM)
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olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
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#ifdef IXGBE_FCOE
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/* use index 1 context for FCOE/FSO */
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if (tx_flags & IXGBE_TX_FLAGS_FCOE)
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olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
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(1 << IXGBE_ADVTXD_IDX_SHIFT));
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#endif
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return olinfo_status;
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}
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#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
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IXGBE_TXD_CMD_RS)
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static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
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struct sk_buff *skb,
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struct ixgbe_tx_buffer *first,
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u32 tx_flags,
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const u8 hdr_len)
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{
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struct device *dev = tx_ring->dev;
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struct ixgbe_tx_buffer *tx_buffer_info;
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unsigned int len;
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unsigned int total = skb->len;
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unsigned int offset = 0, size, count = 0;
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unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
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unsigned int f;
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unsigned int bytecount = skb->len;
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u16 gso_segs = 1;
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u16 i;
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union ixgbe_adv_tx_desc *tx_desc;
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dma_addr_t dma;
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__le32 cmd_type, olinfo_status;
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struct skb_frag_struct *frag;
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unsigned int f = 0;
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unsigned int data_len = skb->data_len;
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unsigned int size = skb_headlen(skb);
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u32 offset = 0;
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u32 paylen = skb->len - hdr_len;
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u16 i = tx_ring->next_to_use;
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u16 gso_segs;
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i = tx_ring->next_to_use;
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#ifdef IXGBE_FCOE
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if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
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if (data_len >= sizeof(struct fcoe_crc_eof)) {
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data_len -= sizeof(struct fcoe_crc_eof);
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} else {
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size -= sizeof(struct fcoe_crc_eof) - data_len;
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data_len = 0;
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}
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}
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if (tx_flags & IXGBE_TX_FLAGS_FCOE)
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/* excluding fcoe_crc_eof for FCoE */
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total -= sizeof(struct fcoe_crc_eof);
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len = min(skb_headlen(skb), total);
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while (len) {
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
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tx_buffer_info->length = size;
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tx_buffer_info->mapped_as_page = false;
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tx_buffer_info->dma = dma_map_single(dev,
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skb->data + offset,
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size, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, tx_buffer_info->dma))
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#endif
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dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma))
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goto dma_error;
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tx_buffer_info->time_stamp = jiffies;
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tx_buffer_info->next_to_watch = i;
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len -= size;
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total -= size;
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offset += size;
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count++;
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cmd_type = ixgbe_tx_cmd_type(tx_flags);
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olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
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if (len) {
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
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for (;;) {
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while (size > IXGBE_MAX_DATA_PER_TXD) {
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tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
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tx_desc->read.cmd_type_len =
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cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
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tx_desc->read.olinfo_status = olinfo_status;
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offset += IXGBE_MAX_DATA_PER_TXD;
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size -= IXGBE_MAX_DATA_PER_TXD;
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tx_desc++;
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i++;
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if (i == tx_ring->count)
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if (i == tx_ring->count) {
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
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i = 0;
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}
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}
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for (f = 0; f < nr_frags; f++) {
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struct skb_frag_struct *frag;
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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tx_buffer_info->length = offset + size;
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tx_buffer_info->tx_flags = tx_flags;
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tx_buffer_info->dma = dma;
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tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
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tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
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tx_desc->read.olinfo_status = olinfo_status;
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if (!data_len)
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break;
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frag = &skb_shinfo(skb)->frags[f];
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len = min((unsigned int)frag->size, total);
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offset = frag->page_offset;
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#ifdef IXGBE_FCOE
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size = min_t(unsigned int, data_len, frag->size);
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#else
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size = frag->size;
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#endif
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data_len -= size;
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f++;
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offset = 0;
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tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
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dma = dma_map_page(dev, frag->page, frag->page_offset,
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size, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma))
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goto dma_error;
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tx_desc++;
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i++;
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if (i == tx_ring->count) {
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tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
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i = 0;
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}
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}
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tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
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while (len) {
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i++;
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if (i == tx_ring->count)
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i = 0;
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
|
||||
size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
|
||||
|
||||
tx_buffer_info->length = size;
|
||||
tx_buffer_info->dma = dma_map_page(dev,
|
||||
frag->page,
|
||||
offset, size,
|
||||
DMA_TO_DEVICE);
|
||||
tx_buffer_info->mapped_as_page = true;
|
||||
if (dma_mapping_error(dev, tx_buffer_info->dma))
|
||||
goto dma_error;
|
||||
tx_buffer_info->time_stamp = jiffies;
|
||||
tx_buffer_info->next_to_watch = i;
|
||||
|
||||
len -= size;
|
||||
total -= size;
|
||||
offset += size;
|
||||
count++;
|
||||
}
|
||||
if (total == 0)
|
||||
break;
|
||||
}
|
||||
tx_ring->next_to_use = i;
|
||||
|
||||
if (tx_flags & IXGBE_TX_FLAGS_TSO)
|
||||
gso_segs = skb_shinfo(skb)->gso_segs;
|
||||
|
|
@ -6498,93 +6589,16 @@ static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
|
|||
gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
|
||||
skb_shinfo(skb)->gso_size);
|
||||
#endif /* IXGBE_FCOE */
|
||||
bytecount += (gso_segs - 1) * hdr_len;
|
||||
else
|
||||
gso_segs = 1;
|
||||
|
||||
/* multiply data chunks by size of headers */
|
||||
tx_ring->tx_buffer_info[i].bytecount = bytecount;
|
||||
tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
|
||||
tx_ring->tx_buffer_info[i].skb = skb;
|
||||
tx_ring->tx_buffer_info[first].next_to_watch = i;
|
||||
tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
|
||||
tx_buffer_info->gso_segs = gso_segs;
|
||||
tx_buffer_info->skb = skb;
|
||||
|
||||
return count;
|
||||
|
||||
dma_error:
|
||||
e_dev_err("TX DMA map failed\n");
|
||||
|
||||
/* clear timestamp and dma mappings for failed tx_buffer_info map */
|
||||
tx_buffer_info->dma = 0;
|
||||
tx_buffer_info->time_stamp = 0;
|
||||
tx_buffer_info->next_to_watch = 0;
|
||||
if (count)
|
||||
count--;
|
||||
|
||||
/* clear timestamp and dma mappings for remaining portion of packet */
|
||||
while (count--) {
|
||||
if (i == 0)
|
||||
i += tx_ring->count;
|
||||
i--;
|
||||
tx_buffer_info = &tx_ring->tx_buffer_info[i];
|
||||
ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
|
||||
int tx_flags, int count, u32 paylen, u8 hdr_len)
|
||||
{
|
||||
union ixgbe_adv_tx_desc *tx_desc = NULL;
|
||||
struct ixgbe_tx_buffer *tx_buffer_info;
|
||||
u32 olinfo_status = 0, cmd_type_len = 0;
|
||||
unsigned int i;
|
||||
u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
|
||||
|
||||
cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
|
||||
|
||||
cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
|
||||
|
||||
if (tx_flags & IXGBE_TX_FLAGS_VLAN)
|
||||
cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
|
||||
|
||||
if (tx_flags & IXGBE_TX_FLAGS_TSO) {
|
||||
cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
|
||||
|
||||
olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
|
||||
IXGBE_ADVTXD_POPTS_SHIFT;
|
||||
|
||||
/* use index 1 context for tso */
|
||||
olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
|
||||
if (tx_flags & IXGBE_TX_FLAGS_IPV4)
|
||||
olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
|
||||
IXGBE_ADVTXD_POPTS_SHIFT;
|
||||
|
||||
} else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
|
||||
olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
|
||||
IXGBE_ADVTXD_POPTS_SHIFT;
|
||||
|
||||
if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
|
||||
olinfo_status |= IXGBE_ADVTXD_CC;
|
||||
olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
|
||||
if (tx_flags & IXGBE_TX_FLAGS_FSO)
|
||||
cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
|
||||
}
|
||||
|
||||
olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
|
||||
|
||||
i = tx_ring->next_to_use;
|
||||
while (count--) {
|
||||
tx_buffer_info = &tx_ring->tx_buffer_info[i];
|
||||
tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
|
||||
tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
|
||||
tx_desc->read.cmd_type_len =
|
||||
cpu_to_le32(cmd_type_len | tx_buffer_info->length);
|
||||
tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
|
||||
i++;
|
||||
if (i == tx_ring->count)
|
||||
i = 0;
|
||||
}
|
||||
|
||||
tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
|
||||
/* set the timestamp */
|
||||
first->time_stamp = jiffies;
|
||||
|
||||
/*
|
||||
* Force memory writes to complete before letting h/w
|
||||
|
|
@ -6594,8 +6608,30 @@ static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
|
|||
*/
|
||||
wmb();
|
||||
|
||||
tx_ring->next_to_use = i;
|
||||
/* set next_to_watch value indicating a packet is present */
|
||||
first->next_to_watch = tx_desc;
|
||||
|
||||
/* notify HW of packet */
|
||||
writel(i, tx_ring->tail);
|
||||
|
||||
return;
|
||||
dma_error:
|
||||
dev_err(dev, "TX DMA map failed\n");
|
||||
|
||||
/* clear dma mappings for failed tx_buffer_info map */
|
||||
for (;;) {
|
||||
tx_buffer_info = &tx_ring->tx_buffer_info[i];
|
||||
ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
|
||||
if (tx_buffer_info == first)
|
||||
break;
|
||||
if (i == 0)
|
||||
i = tx_ring->count;
|
||||
i--;
|
||||
}
|
||||
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
tx_ring->next_to_use = i;
|
||||
}
|
||||
|
||||
static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
|
||||
|
|
@ -6742,12 +6778,12 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
|
|||
struct ixgbe_adapter *adapter,
|
||||
struct ixgbe_ring *tx_ring)
|
||||
{
|
||||
struct ixgbe_tx_buffer *first;
|
||||
int tso;
|
||||
u32 tx_flags = 0;
|
||||
#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
|
||||
unsigned short f;
|
||||
#endif
|
||||
u16 first;
|
||||
u16 count = TXD_USE_COUNT(skb_headlen(skb));
|
||||
__be16 protocol;
|
||||
u8 hdr_len = 0;
|
||||
|
|
@ -6796,7 +6832,7 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
|
|||
|
||||
#endif
|
||||
/* record the location of the first descriptor for this packet */
|
||||
first = tx_ring->next_to_use;
|
||||
first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
|
||||
|
||||
if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
|
||||
#ifdef IXGBE_FCOE
|
||||
|
|
@ -6817,22 +6853,16 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
|
|||
tx_flags |= IXGBE_TX_FLAGS_TSO;
|
||||
else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
|
||||
tx_flags |= IXGBE_TX_FLAGS_CSUM;
|
||||
}
|
||||
|
||||
count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
|
||||
if (count) {
|
||||
/* add the ATR filter if ATR is on */
|
||||
if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
|
||||
ixgbe_atr(tx_ring, skb, tx_flags, protocol);
|
||||
ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
|
||||
ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
|
||||
|
||||
} else {
|
||||
tx_ring->tx_buffer_info[first].time_stamp = 0;
|
||||
tx_ring->next_to_use = first;
|
||||
goto out_drop;
|
||||
}
|
||||
|
||||
ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
|
||||
|
||||
ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
|
||||
out_drop:
|
||||
|
|
|
|||
Loading…
Reference in a new issue