drm/radeon: update r600 set/get pcie lane config
Updated to the preferred programming sequence. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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492d2b61b3
commit
d5445a17e7
1 changed files with 15 additions and 42 deletions
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@ -4523,7 +4523,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
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void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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{
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{
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u32 link_width_cntl, mask, target_reg;
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u32 link_width_cntl, mask;
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if (rdev->flags & RADEON_IS_IGP)
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if (rdev->flags & RADEON_IS_IGP)
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return;
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return;
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@ -4535,7 +4535,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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if (ASIC_IS_X2(rdev))
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if (ASIC_IS_X2(rdev))
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return;
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return;
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/* FIXME wait for idle */
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radeon_gui_idle(rdev);
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switch (lanes) {
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switch (lanes) {
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case 0:
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case 0:
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@ -4554,53 +4554,24 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
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mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
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break;
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break;
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case 12:
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case 12:
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/* not actually supported */
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mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
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mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
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break;
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break;
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case 16:
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case 16:
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default:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
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mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
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break;
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break;
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default:
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DRM_ERROR("invalid pcie lane request: %d\n", lanes);
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return;
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}
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}
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link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
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if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
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link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
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(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
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link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
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return;
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R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
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if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
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return;
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link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
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RADEON_PCIE_LC_RECONFIG_NOW |
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R600_PCIE_LC_RENEGOTIATE_EN |
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R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
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link_width_cntl |= mask;
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WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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/* some northbridges can renegotiate the link rather than requiring
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* a complete re-config.
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* e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
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*/
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if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
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link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
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else
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link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
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WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
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RADEON_PCIE_LC_RECONFIG_NOW));
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if (rdev->family >= CHIP_RV770)
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target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
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else
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target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
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/* wait for lane set to complete */
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link_width_cntl = RREG32(target_reg);
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while (link_width_cntl == 0xffffffff)
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link_width_cntl = RREG32(target_reg);
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}
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}
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int r600_get_pcie_lanes(struct radeon_device *rdev)
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int r600_get_pcie_lanes(struct radeon_device *rdev)
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@ -4617,13 +4588,11 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
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if (ASIC_IS_X2(rdev))
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if (ASIC_IS_X2(rdev))
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return 0;
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return 0;
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/* FIXME wait for idle */
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radeon_gui_idle(rdev);
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link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
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switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
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case RADEON_PCIE_LC_LINK_WIDTH_X0:
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return 0;
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case RADEON_PCIE_LC_LINK_WIDTH_X1:
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case RADEON_PCIE_LC_LINK_WIDTH_X1:
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return 1;
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return 1;
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case RADEON_PCIE_LC_LINK_WIDTH_X2:
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case RADEON_PCIE_LC_LINK_WIDTH_X2:
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@ -4632,6 +4601,10 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
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return 4;
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return 4;
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case RADEON_PCIE_LC_LINK_WIDTH_X8:
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case RADEON_PCIE_LC_LINK_WIDTH_X8:
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return 8;
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return 8;
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case RADEON_PCIE_LC_LINK_WIDTH_X12:
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/* not actually supported */
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return 12;
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case RADEON_PCIE_LC_LINK_WIDTH_X0:
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case RADEON_PCIE_LC_LINK_WIDTH_X16:
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case RADEON_PCIE_LC_LINK_WIDTH_X16:
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default:
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default:
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return 16;
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return 16;
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