drm/i915: cleanup rc6 code
Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: checkpatch cleanup] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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1daed3fb83
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d5bb081b02
4 changed files with 75 additions and 46 deletions
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@ -355,10 +355,10 @@ static int i915_drm_thaw(struct drm_device *dev)
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/* Resume the modeset for every activated CRTC */
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/* Resume the modeset for every activated CRTC */
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drm_helper_resume_force_mode(dev);
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drm_helper_resume_force_mode(dev);
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}
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/* Clock gating state */
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if (dev_priv->renderctx && dev_priv->pwrctx)
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intel_enable_clock_gating(dev);
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ironlake_enable_rc6(dev);
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}
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intel_opregion_init(dev);
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intel_opregion_init(dev);
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@ -1260,6 +1260,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
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extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
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extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
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extern bool intel_fbc_enabled(struct drm_device *dev);
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extern bool intel_fbc_enabled(struct drm_device *dev);
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extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
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extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
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extern void ironlake_enable_rc6(struct drm_device *dev);
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extern void gen6_set_rps(struct drm_device *dev, u8 val);
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extern void gen6_set_rps(struct drm_device *dev, u8 val);
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extern void intel_detect_pch (struct drm_device *dev);
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extern void intel_detect_pch (struct drm_device *dev);
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extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
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extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
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@ -822,10 +822,6 @@ int i915_save_state(struct drm_device *dev)
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if (IS_GEN6(dev))
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if (IS_GEN6(dev))
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gen6_disable_rps(dev);
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gen6_disable_rps(dev);
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/* XXX disabling the clock gating breaks suspend on gm45
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intel_disable_clock_gating(dev);
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*/
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/* Cache mode state */
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/* Cache mode state */
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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@ -868,6 +864,9 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE (IMR, dev_priv->saveIMR);
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I915_WRITE (IMR, dev_priv->saveIMR);
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}
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}
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/* Clock gating state */
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intel_enable_clock_gating(dev);
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if (IS_IRONLAKE_M(dev)) {
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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ironlake_enable_drps(dev);
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intel_init_emon(dev);
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intel_init_emon(dev);
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@ -6415,44 +6415,6 @@ void intel_enable_clock_gating(struct drm_device *dev)
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} else if (IS_I830(dev)) {
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} else if (IS_I830(dev)) {
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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}
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}
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/*
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* GPU can automatically power down the render unit if given a page
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* to save state.
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*/
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if (IS_IRONLAKE_M(dev)) {
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if (dev_priv->renderctx == NULL)
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dev_priv->renderctx = intel_alloc_context_page(dev);
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if (dev_priv->renderctx) {
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struct drm_i915_gem_object *obj = dev_priv->renderctx;
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if (BEGIN_LP_RING(6) != 0) {
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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dev_priv->renderctx = NULL;
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return;
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}
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OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
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OUT_RING(MI_SET_CONTEXT);
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OUT_RING(obj->gtt_offset |
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MI_MM_SPACE_GTT |
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MI_SAVE_EXT_STATE_EN |
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MI_RESTORE_EXT_STATE_EN |
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MI_RESTORE_INHIBIT);
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OUT_RING(MI_SUSPEND_FLUSH);
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OUT_RING(MI_NOOP);
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OUT_RING(MI_FLUSH);
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ADVANCE_LP_RING();
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} else
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DRM_DEBUG_KMS("Failed to allocate render context."
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"Disable RC6\n");
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if (dev_priv->pwrctx == NULL)
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dev_priv->pwrctx = intel_alloc_context_page(dev);
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if (dev_priv->pwrctx) {
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struct drm_i915_gem_object *obj = dev_priv->pwrctx;
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I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
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}
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}
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}
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}
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void intel_disable_clock_gating(struct drm_device *dev)
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void intel_disable_clock_gating(struct drm_device *dev)
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@ -6482,6 +6444,57 @@ void intel_disable_clock_gating(struct drm_device *dev)
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}
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}
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}
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}
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static void ironlake_disable_rc6(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
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wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
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10);
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POSTING_READ(CCID);
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I915_WRITE(PWRCTXA, 0);
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POSTING_READ(PWRCTXA);
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
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POSTING_READ(RSTDBYCTL);
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i915_gem_object_unpin(dev_priv->renderctx);
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drm_gem_object_unreference(&dev_priv->renderctx->base);
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dev_priv->renderctx = NULL;
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i915_gem_object_unpin(dev_priv->pwrctx);
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drm_gem_object_unreference(&dev_priv->pwrctx->base);
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dev_priv->pwrctx = NULL;
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}
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void ironlake_enable_rc6(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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/*
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* GPU can automatically power down the render unit if given a page
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* to save state.
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*/
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ret = BEGIN_LP_RING(6);
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if (ret) {
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ironlake_disable_rc6(dev);
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return;
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}
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OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
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OUT_RING(MI_SET_CONTEXT);
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OUT_RING(dev_priv->renderctx->gtt_offset |
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MI_MM_SPACE_GTT |
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MI_SAVE_EXT_STATE_EN |
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MI_RESTORE_EXT_STATE_EN |
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MI_RESTORE_INHIBIT);
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OUT_RING(MI_SUSPEND_FLUSH);
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OUT_RING(MI_NOOP);
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OUT_RING(MI_FLUSH);
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ADVANCE_LP_RING();
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I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
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}
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/* Set up chip specific display functions */
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/* Set up chip specific display functions */
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static void intel_init_display(struct drm_device *dev)
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static void intel_init_display(struct drm_device *dev)
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{
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{
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@ -6724,6 +6737,21 @@ void intel_modeset_init(struct drm_device *dev)
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if (IS_GEN6(dev))
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if (IS_GEN6(dev))
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gen6_enable_rps(dev_priv);
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gen6_enable_rps(dev_priv);
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if (IS_IRONLAKE_M(dev)) {
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dev_priv->renderctx = intel_alloc_context_page(dev);
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if (!dev_priv->renderctx)
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goto skip_rc6;
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dev_priv->pwrctx = intel_alloc_context_page(dev);
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if (!dev_priv->pwrctx) {
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i915_gem_object_unpin(dev_priv->renderctx);
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drm_gem_object_unreference(&dev_priv->renderctx->base);
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dev_priv->renderctx = NULL;
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goto skip_rc6;
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}
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ironlake_enable_rc6(dev);
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}
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skip_rc6:
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INIT_WORK(&dev_priv->idle_work, intel_idle_update);
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INIT_WORK(&dev_priv->idle_work, intel_idle_update);
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setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
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setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
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(unsigned long)dev);
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(unsigned long)dev);
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@ -6760,7 +6788,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
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if (IS_GEN6(dev))
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if (IS_GEN6(dev))
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gen6_disable_rps(dev);
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gen6_disable_rps(dev);
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intel_disable_clock_gating(dev);
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if (IS_IRONLAKE_M(dev))
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ironlake_disable_rc6(dev);
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mutex_unlock(&dev->struct_mutex);
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mutex_unlock(&dev->struct_mutex);
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