i3c: i3c-master-qcom-geni: Handle timeout for DMA FSM reset
This change adds timeout handling scenario for the DMA TX/TX reset sequence and adds the proper error logs. If return value from API wait_for_completion_timeout() is not taken cared, may mislead the debug. Also Fix the issue of not initializing the completion variable during command execution time. Change-Id: I01442e611ea531bbd6124c0b5f4b6c8da9c79281 Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
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1 changed files with 7 additions and 2 deletions
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@ -761,6 +761,7 @@ static int _i3c_geni_execute_command
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enum i3c_trans_dir rnw = gi3c->cur_rnw;
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u32 len = gi3c->cur_len;
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reinit_completion(&gi3c->done);
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geni_se_select_mode(gi3c->se.base, xfer->mode);
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gi3c->err = 0;
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@ -810,8 +811,8 @@ static int _i3c_geni_execute_command
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writel_relaxed(1, gi3c->se.base +
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SE_GENI_TX_WATERMARK_REG);
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}
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time_remaining = wait_for_completion_timeout(&gi3c->done,
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XFER_TIMEOUT);
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time_remaining = wait_for_completion_timeout(&gi3c->done, XFER_TIMEOUT);
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if (!time_remaining) {
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unsigned long flags;
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@ -854,7 +855,11 @@ static int _i3c_geni_execute_command
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else
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writel_relaxed(1, gi3c->se.base +
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SE_DMA_TX_FSM_RST);
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time_remaining =
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wait_for_completion_timeout(&gi3c->done, XFER_TIMEOUT);
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if (!time_remaining)
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"Timeout:FSM Reset, rnw:%d\n", rnw);
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}
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geni_se_rx_dma_unprep(gi3c->se.i3c_rsc.wrapper_dev,
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rx_dma, len);
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