Merge "power: qpnp-qg: Limit max FCC value based on QG subtype"
This commit is contained in:
commit
f03998e3f6
2 changed files with 15 additions and 0 deletions
|
@ -153,6 +153,7 @@ struct qpnp_qg {
|
|||
int ibat_tcss_entry;
|
||||
int soc_tcss;
|
||||
int tcss_entry_count;
|
||||
int max_fcc_limit_ma;
|
||||
u32 fifo_done_count;
|
||||
u32 wa_flags;
|
||||
u32 seq_no;
|
||||
|
|
|
@ -2980,6 +2980,13 @@ static int qg_load_battery_profile(struct qpnp_qg *chip)
|
|||
chip->bp.fastchg_curr_ma = -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Update the max fcc values based on QG subtype including
|
||||
* error margins.
|
||||
*/
|
||||
chip->bp.fastchg_curr_ma = min(chip->max_fcc_limit_ma,
|
||||
chip->bp.fastchg_curr_ma);
|
||||
|
||||
rc = of_property_read_u32(profile_node, "qcom,qg-batt-profile-ver",
|
||||
&chip->bp.qg_profile_version);
|
||||
if (rc < 0) {
|
||||
|
@ -3354,6 +3361,8 @@ static int qg_sanitize_sdam(struct qpnp_qg *chip)
|
|||
}
|
||||
|
||||
#define ADC_CONV_DLY_512MS 0xA
|
||||
#define IBAT_5A_FCC_MA 4800
|
||||
#define IBAT_10A_FCC_MA 9600
|
||||
static int qg_hw_init(struct qpnp_qg *chip)
|
||||
{
|
||||
int rc, temp;
|
||||
|
@ -3367,6 +3376,11 @@ static int qg_hw_init(struct qpnp_qg *chip)
|
|||
return rc;
|
||||
}
|
||||
|
||||
if (chip->qg_subtype == QG_ADC_IBAT_5A)
|
||||
chip->max_fcc_limit_ma = IBAT_5A_FCC_MA;
|
||||
else
|
||||
chip->max_fcc_limit_ma = IBAT_10A_FCC_MA;
|
||||
|
||||
rc = qg_set_wa_flags(chip);
|
||||
if (rc < 0) {
|
||||
pr_err("Failed to update PMIC type flags, rc=%d\n", rc);
|
||||
|
|
Loading…
Reference in a new issue