Commit graph

420 commits

Author SHA1 Message Date
Paul Walmsley
3dc2197579 OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST register
OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits
are in CM_{I,F}CLKEN2_CORE [1].  Fix by implementing a custom clkops
.find_idlest function to return the correct slave IDLEST register.

...

1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1
   (Rev. V) Technical Reference Manual, tables 4-99 and 4-105.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:36 -06:00
Paul Walmsley
72350b29a4 OMAP2/3 clock: split, rename omap2_wait_clock_ready()
Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not
handled by the current omap2_wait_clock_ready() code.  In preparation
for patches that fix the unusual devices, rename the function
omap2_wait_clock_ready() to omap2_wait_module_ready() and split it
into three parts:

1. A clkops-specific companion clock return function (by default,
   omap2_clk_dflt_find_companion())

2. A clkops-specific CM_IDLEST register address and bit shift return
   function (by default, omap2_clk_dflt_find_idlest())

3. Code to wait for the CM to indicate that the module is ready
   (omap2_cm_wait_idlest())

Clocks can now specify their own custom find_companion() and find_idlest()
functions; used in subsequent patches.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:35 -06:00
Rajendra Nayak
df56556e57 OMAP3 SDRC: Move the clk stabilization delay to the right place
The clock stabilization delay post a M2 divider change is needed
even before a SDRC interface clock re-enable and not only before
jumping back to SDRAM.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:35 -06:00
Rajendra Nayak
8ff120e530 OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze.  The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.

Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
2009-07-24 20:10:35 -06:00
Paul Walmsley
75f251e3d0 OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot
Stop setting SDRC_POWER.PWDENA on boot.  There is a nasty erratum
(34xx erratum 1.150) that can cause memory corruption if PWDENA is
enabled.

Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>.

Tested on BeagleBoard rev C2.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
2009-07-24 19:44:01 -06:00
Jean Pihet
9fb97412c3 OMAP3: Setup MUX settings for SDRC CKE signals
This patches ensures the MUX settings are correct for the SDRC
CKE signals to SDRAM. This allows the self-refresh to work when
2 chip-selects are in use.

A warning is thrown away in case the initial muxing is incorrect,
in order to track faulty or old-dated bootloaders.
Note: The CONFIG_OMAP_MUX and CONFIG_OMAP_MUX_WARNINGS options
must be enabled for the mux code to have effect.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 19:43:25 -06:00
Jean Pihet
58cda884ec OMAP3 SDRC: add support for 2 SDRAM chip selects
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.

This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 19:43:25 -06:00
Adrian Hunter
c8e6488f7b OMAP3: RX51: Use OneNAND sync read / write
Use OneNAND sync read / write

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:25 +03:00
Adrian Hunter
6d453e84b5 OMAP2/3: gpmc-onenand: correct use of async timings
Use async timings when sync timings are not requested.

Also ensure that OneNAND is in async mode when async
timings are used.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:24 +03:00
Kevin Hilman
8e25ad964a OMAP2/3: Add omap_type() for determining GP/EMU/HS
The omap_type() function is added and returns the DEVICETYPE field of
the CONTROL_STATUS register.  The result can be used for conditional
code based on whether device is GP (general purpose), EMU or
HS (high security). Also move the type defines so omap1 code
compile does not require ifdefs for sections using these defines.

This code is needed for the following fix to set the SRAM
size correctly for HS omaps.  Also at least PM and watchdog
code will need this function.

Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:23 +03:00
Roel Kluin
091a58af0b OMAP2/3: omap mailbox: platform_get_irq() error ignored
platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq
is unsigned, so the error was not noticed.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:22 +03:00
Grazvydas Ignotas
762ad3a476 OMAP2/3: mmc-twl4030: use correct controller in twl_mmc23_set_power
twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which
breaks MMC3. Find the right controller to use instead.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:22 +03:00
Russell King
312cec5d09 Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into devel 2009-06-20 10:57:40 +01:00
Roel Kluin
2687069f3a OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons
with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1
after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley
7b7bcefa35 OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
Correspondence with the TI OMAP hardware team indicates that
SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f.  This number
was apparently derived from process validation.  This is only used
when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
83MHz).

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Tero Kristo
3afec6332e OMAP3: Add support for DPLL3 divisor values higher than 2
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley
df14e4747a OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
Convert omap3_sram_configure_core_dpll() to use macros rather than
magic numbers.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley
4267b5d152 OMAP3 SRAM: add more comments on the SRAM code
Clean up comments and copyrights on the CORE DPLL3 M2 divider change code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley
d0ba3922ae OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley
c9812d042a OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley
2f135eaf18 OMAP3 clock: initialize SDRC timings at kernel start
On the OMAP3, initialize SDRC timings when the kernel boots.  This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:30 -06:00
Paul Walmsley
6adb8f388e OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider.  This does not appear
to be necessary.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:30 -06:00
Santosh Shilimkar
934f8be7b1 ARM: OMAP4: SMP: Enable SMP support for OMAP4430
This patch enables SMP on OMAP4430 SDP platform.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:04:06 +05:30
Santosh Shilimkar
39e1d4c18f ARM: OMAP4: SMP: Add mpu timer support for OMAP4430
This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:03:59 +05:30
Santosh Shilimkar
367cd31ee0 ARM: OMAP4: SMP: Add OMAP4430 SMP board files
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430
SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC
with GIC used for interrupt handling and SCU for cache coherency.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:03:50 +05:30
Russell King
949abd84cd Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel
Conflicts:
	arch/arm/Makefile
2009-05-29 20:03:43 +01:00
Russell King
42f1d2e06a Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel 2009-05-29 10:04:24 +01:00
Tony Lindgren
cd07ecc828 Merge branch 'omap4' into for-next 2009-05-28 15:45:14 -07:00
Tony Lindgren
4c50d22a0c Merge branch 'omap3-boards' into for-next 2009-05-28 15:45:07 -07:00
Tony Lindgren
970a724d91 Merge branch 'omap3-upstream' into for-next
Conflicts:
	arch/arm/mach-omap2/serial.c
2009-05-28 15:44:54 -07:00
Tony Lindgren
c81592ba1b Merge branch 'omap-upstream' into for-next
Conflicts:
	arch/arm/mach-omap2/Makefile
2009-05-28 15:41:03 -07:00
Santosh Shilimkar
46ba0abfe1 ARM: OMAP4: Add support for 4430 SDP
This patch updates the Makefile and Kconfig entries for OMAP4. The OMAP4430 SDP
board file supports only minimal set of drivers.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:16:05 -07:00
Santosh Shilimkar
44169075e6 ARM: OMAP4: Add minimal support for omap4
This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.

OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:16:04 -07:00
Grazvydas Ignotas
7419045016 ARM: OMAP3: pandora: add support for mode devices
Add support for keypad, GPIO keys and LEDs. Also enable hardware
debounce feature for GPIO keys.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:15:44 -07:00
Syed Mohammed Khasim
53c5ec31e7 ARM: OMAP3: Add omap3 EVM support
Add omap3 EVM support

Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:13:28 -07:00
Vikram Pandita
577145f454 ARM: OMAP3: Add support for OMAP3 Zoom2 board
This patch creates the minimal OMAP3 Zoom2 board support.

Signed-off-by: Mikkel Christensen <mlc@ti.com>
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:04 -07:00
Adrian Hunter
f52eeee83d ARM: OMAP3: RX51: Connect VAUX3 to MMC2
Connect VAUX3 to MMC2

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:04 -07:00
Grazvydas Ignotas
64f535a87c ARM: OMAP3: pandora: setup regulator framework for MMC
Setup regulators for MMC1 and MMC2 to get those SD slots
working again.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
CC: David Brownell <david-b@pacbell.net>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:04 -07:00
David Brownell
bb3b9d8eb9 ARM: OMAP3: Initialize regulators for Beagle and Overo
Initialize regulators for Beagle and Overo.

Patch is based on earlier patches posted to linux-omap mailing
list.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:03 -07:00
David Brownell
b583f26d51 ARM: OMAP3: mmc-twl4030 uses regulator framework
Decouple the HSMMC glue from the twl4030 as the only
regulator provider, using the regulator framework instead.
This makes the glue's "mmc-twl4030" name become a complete
misnomer ... this code could probably all migrate into the
HSMMC driver now.

Tested on 3430SDP (SD and low-voltage MMC) and Beagle (SD),
plus some other boards (including Overo) after they were
converted to set up MMC regulators properly.

Eventually all boards should just associate a regulator with
each MMC controller they use.  In some cases (Overo MMC2 and
Pandora MMC3, at least) that would be a fixed-voltage regulator
with no real software control.  As a temporary hack (pending
regulator-next updates to make the "fixed.c" regulator become
usable) there's a new ocr_mask field for those boards.

Patch updated with a fix for disabling vcc_aux by
Adrian Hunter <adrian.hunter@nokia.com>

Cc: Pierre Ossman <drzeus-list@drzeus.cx>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:03 -07:00
Tony Lindgren
4a899d5e93 ARM: OMAP3: Initialize more devices for LDP
Based on an earlier patches by Stanley.Miao <stanley.miao@windriver.com>
and Nishant Kamat <nskamat@ti.com>.

Note that at the ads7846 support still needs support for vaux_control
for the touchscreen to work.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:00 -07:00
Imre Deak
49adf465d2 ARM: OMAP3: ZOOM MDK: Add FB support to board file
Based on an earlier patch by Stanley.Miao <stanley.miao@windriver.com>
with board-*.c changes split to avoid conflicts with other device updates.

Cc: linux-fbdev-devel@lists.sourceforge.net
Signed-off-by: Stanley.Miao <stanley.miao@windriver.com>
Signed-off-by: Imre Deak <imre.deak@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:04:00 -07:00
Paul Walmsley
17a722caae ARM: OMAP3: SDRC: add timing data for Qimonda HYB18M512160AF-6
Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on
the OMAP3430SDP boards.

Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chip used on 3430SDP.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:03:59 -07:00
Paul Walmsley
2e12bd7ef1 ARM: OMAP3: SDRC: add timing data for Micron MT46H32M32LF-6, v2
Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the
OMAP3 Beagle and EVM boards.  Original timing data is from the Micron
datasheet PDF downloaded from:

http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf

Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chips used on Beagle & OMAP3EVM.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:03:59 -07:00
Vikram Pandita
2aa57be2d9 ARM: OMAP2/3: Serial: Remove arch_initcall dependency
Move platform_device_register() for serial device to
omap_serial_init()

There is no need to have arch_initcall() dependency in serial
as already board files call the function omap_serial_init()

Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 14:03:59 -07:00
Imre Deak
7d8e967f88 ARM: OMAP2: 2430SDP: Add FB support to board file
Based on an earlier patch by Hunyue Yau <hyau@mvista.com> with
board-*.c changes split to avoid conflicts with other device updates.

Cc: linux-fbdev-devel@lists.sourceforge.net
Signed-off-by: Hunyue Yau <hyau@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Imre Deak <imre.deak@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 13:23:53 -07:00
Tony Lindgren
1a48e15751 ARM: OMAP2/3: Add generic smc91x support when connected to GPMC
Convert the board-rx51 smc91x code to be generic and make
the boards to use it. This allows future recalculation of the
timings when the source clock gets scaled.

Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL.

Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing
calculations.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 13:23:52 -07:00
Juha Yrjola
aa62e90fe0 ARM: OMAP2/3: Add generic onenand support when connected to GPMC
Add generic onenand support when connected to GPMC and make the
boards to use it.

The patch has been modified to make it more generic to support all
the boards with GPMC. The patch also remove unused prototype for
omap2_onenand_rephase(void).

Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC
and setting the GPMC timings in the bootloader. Setting the GPMC
timings in the bootloader will not allow supporting frequency
scaling for the onenand source clock.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-28 13:23:52 -07:00
Kevin Hilman
d3fd3290c4 OMAP3: PM: prevent module wakeups from waking IVA2
By default, prevent functional wakeups from inside a module from
waking up the IVA2.  Let DSP Bridge code handle this when loaded.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 10:59:10 -07:00
Kevin Hilman
b1340d17d2 OMAP3: PM: Clear pending PRCM reset flags on init
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 10:59:10 -07:00