Commit graph

54 commits

Author SHA1 Message Date
Arun Sharma
60063497a9 atomic: use <linux/atomic.h>
This allows us to move duplicated code in <asm/atomic.h>
(atomic_inc_not_zero() for now) to <linux/atomic.h>

Signed-off-by: Arun Sharma <asharma@fb.com>
Reviewed-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: David Miller <davem@davemloft.net>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-07-26 16:49:47 -07:00
David Howells
2e65d1f6ee MN10300: Fix one of the kernel debugger cacheflush variants
One of the kernel debugger cacheflush variants escaped proper testing.  Two of
the labels are wrong, being derived from the code that was copied to construct
the variant.

The first label results in the following assembler message:

    AS      arch/mn10300/mm/cache-dbg-flush-by-reg.o
  arch/mn10300/mm/cache-dbg-flush-by-reg.S: Assembler messages:
  arch/mn10300/mm/cache-dbg-flush-by-reg.S:123: Error: symbol `debugger_local_cache_flushinv_no_dcache' is already defined

And the second label results in the following linker message:

  arch/mn10300/mm/built-in.o:(.text+0x1d39): undefined reference to `mn10300_local_icache_inv_range_reg_end'
  arch/mn10300/mm/built-in.o:(.text+0x1d39): relocation truncated to fit: R_MN10300_PCREL16 against undefined symbol `mn10300_local_icache_inv_range_reg_end'

To test this file the following configuration pieces must be set:

	CONFIG_AM34=y
	CONFIG_MN10300_CACHE_WBACK=y
	CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG=y
	CONFIG_MN10300_CACHE_MANAGE_BY_REG=y
	CONFIG_AM34_HAS_CACHE_SNOOP=n

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-06-07 19:03:52 -07:00
KOSAKI Motohiro
8ea9716fd6 mn10300: convert old cpumask API into new one
Adapt to the new API.

We plan to remove old cpumask APIs later.  Thus this patch converts them
into the new one.

Signed-off-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-05-25 08:39:39 -07:00
Peter Zijlstra
1c39517696 mm: now that all old mmu_gather code is gone, remove the storage
Fold all the mmu_gather rework patches into one for submission

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Reported-by: Hugh Dickins <hughd@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Miller <davem@davemloft.net>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Tony Luck <tony.luck@intel.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: Mel Gorman <mel@csn.ul.ie>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: Nick Piggin <npiggin@kernel.dk>
Cc: Namhyung Kim <namhyung@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-05-25 08:39:16 -07:00
David Howells
67ddb4052d MN10300: Create generic kernel debugger hooks
Create generic kernel debugger hooks in the MN10300 arch and make gdbstub use
them.  This is a preparation for KGDB support.

Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 16:54:30 +00:00
David Howells
7f386ac327 MN10300: Create general kernel debugger cache flushing
Create general kernel debugger cache flushing for MN10300 and get rid of the
old stuff that gdbstub was using.

Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 16:54:30 +00:00
David Howells
b75bb2365d MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly.  The same goes for the dcache invalidation, but this isn't used much.

Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.

The AM33 manual states that:

	An operation that invalidates the cache, switches the writing mode, or
	changes the way mode must be performed after disabling the cache,
	checking the busy bit, and confirming that the cache is not in
	operation.

for the dcache [sec 2.8.3.2.1].  This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.

Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.

Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.

Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-18 16:54:29 +00:00
David Howells
dcca52c21e MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist
The invalidate-only versions of flush_icache_*range() are trying sending the
SMP_ICACHE_INV_FLUSH_RANGE IPI command in SMP kernels when they should be
sending SMP_ICACHE_INV_RANGE as the former does not exist.

Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-14 14:45:29 +00:00
Mark Salter
5a226c6f5c MN10300: Map userspace atomic op regs as a vmalloc page
The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures.  However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.

One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.

glibc is hardcoded to expect the registers to be there.

The way atomic ops are done through these registers is straightforward:

 (1) Write the address of the word you wish to access into AARU.  This causes
     the CPU to go and fetch that word and load it into ADRU.  The status bits
     are also cleared in ASRU.

 (2) The current data value is read from the ADRU register and modified.

 (3) To alter the data in RAM, the revised data is written back to the ADRU
     register, which causes the CPU to attempt to write it back.

 (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
     ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
     must be checked to confirm that the operation wasn't aborted.  If any of
     the watches have been set to true, the operation was aborted.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:56 +01:00
Akira Takeuchi
368dd5acd1 MN10300: And Panasonic AM34 subarch and implement SMP
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300.  Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:55 +01:00
Akira Takeuchi
965ea4bbb9 MN10300: SMP TLB flushing
Implement global TLB flushing for MN10300.  This will be used by the AM34 which
is SMP capable.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:51 +01:00
Akira Takeuchi
dccbf4853a MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits
are a more suitable layout.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:50 +01:00
Akira Takeuchi
a9bc60ebfd MN10300: Make the use of PIDR to mark TLB entries controllable
Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:49 +01:00
David Howells
492e675116 MN10300: Rename __flush_tlb*() to local_flush_tlb*()
Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready
to differentiate local from global TLB flushes when SMP is introduced.

Whilst we're at it, get rid of __flush_tlb_global() and make
local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:49 +01:00
Akira Takeuchi
8f19e3daf3 MN10300: AM34 erratum requires MMUCTR read and write on exception entry
An AM34 erratum requires MMUCTR read and write on entry to certain exceptions,
prior to EPSW.NMID being cleared to allow NMIs to happen.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:48 +01:00
Akira Takeuchi
8be0628923 MN10300: Cache: Implement SMP global cache flushing
Implement SMP global cache flushing for MN10300.  This will be used by the AM34
which is SMP capable.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:47 +01:00
David Howells
b478491f26 MN10300: Allow some cacheflushes to be avoided if cache snooping is available
The AM34 core is able to do cache snooping, and so can skip some of the cache
flushing.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:46 +01:00
Akira Takeuchi
9731d23710 MN10300: AM34: Add cacheflushing by using the AM34 purge registers
The AM34 CPU core provides an automated way of purging the cache rather than
manually iterating over all the tags in the cache.  Make it possible to use
these.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:45 +01:00
Akira Takeuchi
0bd3eb6ca7 MN10300: SMP: Differentiate local cache flushing
Differentiate local cache flushing from global cache flushing so that they can
be done differently on SMP systems.

Rename the cache functions from:

	mn10300_[id]cache_*()

to:

	mn10300_[id]_localcache_*()

and on a UP system, assign the global labels to the local labels.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:45 +01:00
Akira Takeuchi
9b287bf992 MN10300: Cacheflush functions should take unsigned long addresses
The functions that perform cache flushing should take addresses of unsigned
long type, not unsigned int.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:44 +01:00
David Howells
518d4bb746 MN10300: AM34: The current cacheflush routines operate by controlling tag regs
The current cache flush and invalidate routines operate by controlling the
cache tag registers.  Rename the files and add config items to select them.

This makes it easier to support the use of other cache flush methods instead,
such as the use of AM34's area purge registers, if available.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:43 +01:00
David Howells
344af921e6 MN10300: Provide a MN10300_CACHE_ENABLED config option
Provide a MN10300_CACHE_ENABLED config option as inverted logic of
MN10300_CACHE_DISABLED to make things simpler.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:42 +01:00
David Howells
0bc42d7fcb MN10300: Cache: Split cache bits out of arch Kconfig
Split the cache bits out of arch/mn10300/Kconfig as they're quite complex.

Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:41 +01:00
Akira Takeuchi
86c0f935c1 MN10300: Remove monitor/JTAG functions
Remove the monitor trap function and the set_jtag_stub function as they're not
really necessary.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:41 +01:00
Stoyan Gaydarov
292aa14127 MN10300: BUG to BUG_ON changes
Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:33 +01:00
David Howells
57cf4f78c6 MN10300: Fix flush_icache_range()
flush_icache_range() is given virtual addresses to describe the region.  It
deals with these by attempting to translate them through the current set of
page tables.

This is fine for userspace memory and vmalloc()'d areas as they are governed by
page tables.  However, since the regions above 0x80000000 aren't translated
through the page tables by the MMU, the kernel doesn't bother to set up page
tables for them (see paging_init()).

This means flush_icache_range() as it stands cannot be used to flush regions of
the VM area between 0x80000000 and 0x9fffffff where the kernel resides if the
data cache is operating in WriteBack mode.

To fix this, make flush_icache_range() first check for addresses in the upper
half of VM space and deal with them appropriately, before dealing with any
range in the page table mapped area.

Ordinarily, this is not a problem, but it has the capacity to make kprobes and
kgdb malfunction.  It should not affect gdbstub, signal frame setup or module
loading as gdb has its own flush functions, and the others take place in the
page table mapped area only.

Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-01 15:01:47 -07:00
David Howells
62bdb288bf MN10300: Handle missing sys_cacheflush() when caching disabled
When caching is disabled on the MN10300 arch, the sys_cacheflush()
function is removed by conditional stuff in the makefiles, but is still
referred to by the syscall table.

Provide a null version that just returns 0 when caching is disabled (or
-EINVAL if the arguments are silly).

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-09-28 18:01:14 -07:00
Julia Lawall
6e0c64f4dd arch/mn10300/mm: eliminate NULL dereference
dev_name always dereferences its argument, so it should not be called if
the argument is NULL.  The function indeed later tests the argument for
being NULL.

The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)

  // <smpl>
  @@
  expression dev,E;
  @@

  *dev_name(dev)
  ... when != dev = E
  (
  *dev == NULL
  |
  *dev != NULL
  )
  // </smpl>

Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-08-23 11:41:24 -07:00
Nick Piggin
c421b08ef5 mn10300: invoke oom-killer from page fault
As explained in commit 1c0fe6e3bd ("mm: invoke oom-killer from page
fault") , we want to call the architecture independent oom killer when
getting an unexplained OOM from handle_mm_fault, rather than simply
killing current.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: David Rientjes <rientjes@google.com>
Acked-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-06-04 15:21:44 -07:00
Tejun Heo
5a0e3ad6af include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.

Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-30 22:02:32 +09:00
Russell King
4b3073e1c5 MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change

  Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>

Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-20 16:41:46 +00:00
David Howells
012c79bad5 mn10300: make the ASB2305's PCnet32 NIC work by using the PCI bridge's SRAM
Access to the ASB2305's PCnet32 NIC doesn't work correctly because when
the NIC attempts to update the ring buffer flags by DMA, the change to RAM
crops up about 17uS after the interrupt line is asserted.  This is almost
certainly due to a bug in the PCI bridge FPGA on that board.

We can get around this by making dma_alloc_coherent() put the ring buffer
in the SRAM attached to the PCI bridge rather than in the SDRAM.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-01-11 09:34:10 -08:00
Mark Salter
d6bb7a1ad3 mn10300: add cc clobbers to asm statements
gcc 4.2.1 for MN10300 is more agressive than the older gcc in
reordering/moving other insns between an insn that sets flags and an insn
that uses those flags.  This leads to trouble with asm statements which
are missing an explicit "cc" clobber.  This patch adds the explicit "cc"
clobber to asm statements which do indeed clobber the condition flags.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-01-11 09:34:10 -08:00
Andreas Fenkart
4b529401c5 mm: make totalhigh_pages unsigned long
Makes it consistent with the extern declaration, used when CONFIG_HIGHMEM
is set Removes redundant casts in printout messages

Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Cc: Lennox Wu <lennox.wu@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-01-11 09:34:03 -08:00
Geert Uytterhoeven
cc013a8890 arches: drop superfluous casts in nr_free_pages() callers
Commit 9617729941 ("Drop free_pages()")
modified nr_free_pages() to return 'unsigned long' instead of 'unsigned
int'.  This made the casts to 'unsigned long' in most callers superfluous,
so remove them.

[akpm@linux-foundation.org: coding-style fixes]
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Reviewed-by: Christoph Lameter <cl@linux-foundation.org>
Acked-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Kyle McMartin <kyle@mcmartin.ca>
Acked-by: WANG Cong <xiyou.wangcong@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Mikael Starvik <starvik@axis.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Howells <dhowells@redhat.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Chris Zankel <zankel@tensilica.com>
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-09-22 07:17:34 -07:00
Alexey Dobriyan
405f55712d headers: smp_lock.h redux
* Remove smp_lock.h from files which don't need it (including some headers!)
* Add smp_lock.h to files which do need it
* Make smp_lock.h include conditional in hardirq.h
  It's needed only for one kernel_locked() usage which is under CONFIG_PREEMPT

  This will make hardirq.h inclusion cheaper for every PREEMPT=n config
  (which includes allmodconfig/allyesconfig, BTW)

Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-12 12:22:34 -07:00
Linus Torvalds
d06063cc22 Move FAULT_FLAG_xyz into handle_mm_fault() callers
This allows the callers to now pass down the full set of FAULT_FLAG_xyz
flags to handle_mm_fault().  All callers have been (mechanically)
converted to the new calling convention, there's almost certainly room
for architectures to clean up their code and then add FAULT_FLAG_RETRY
when that support is added.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-21 13:08:22 -07:00
David Howells
fd4f683d04 MN10300: Don't set the dirty bit in the DTLB entries in the TLB-miss handler
Remove the special handling for the Data TLB entry dirty bit in the TLB-miss
handler.  As the code stands, all that it does is to cause us to take a second
data address exception to set the dirty bit.  Instead, we can just let
pte_mkdirty() set the bit.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-11 09:02:20 -07:00
David Howells
58a47481b6 MN10300: Don't do misalignment handling for userspace
Don't do misalignment handling for userspace misalignment faults: just
generate an appropriate SIGBUS instead.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:18 -08:00
David Howells
bd9384a9fd MN10300: Don't handle misaligned loading and storing of SP
Don't handle the misaligned loading and storing of the SP register as in C code
that's most certainly a compiler bug.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:18 -08:00
David Howells
d3bd462865 MN10300: Handle misaligned SP-based operands
Support misalignment handling for instructions that have kernel SP-based
address operands, including fixing those that include IMM8 or IMM16
displacements.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:18 -08:00
David Howells
852c15b736 MN10300: Fix misaligned index-register addressing handling
Fix misalignment handling for an address calculated from the sum of two
registers.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
6d615c78fb MN10300: Handle misaligned postinc-with-imm addressing mode correctly
Correctly handle misalignment in MOV instructions with postinc-with-immediate
addressing mode operands.  In these, the immediate value is the increment to
be applied the address register, not the displacement to the address.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
ddb6d05cba MN10300: Perform misalignment fixups of MOV_Lcc
Perform misalignment fixups of the MOV_Lcc instructions (move postinc memory
to register and conditionally loop).

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
aefefbbec1 MN10300: Allow misalignment fixup in interrupt handling
Allow misalignment fixup in interrupt handling in the MN10300 arch.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
f911c685d6 MN10300: Fix register-postinc addressing misalignment handling
Fix misalignment handling of operands with register postincrement addressing.
The flag to indicate that postincrement is required should not be interpreted
as an specification of a value to be added to the address.

Also add BUGs to catch unimplemented parameter markings in the opcodes table.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
b308bf3be1 MN10300: Extract the displacement from an insn correctly in misalignment fixup
Extract the displacement from an MN10300 instruction correctly in the
misalignment fixup handler.

The code should extract the displacement in LSB order, not MSB order.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
ee6e740cf7 MN10300: Add further misalignment fixups
Add further misalignment fixup support to the MN10300 arch, notably for ABS32
and SP+disp addressing.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
9f55588968 MN10300: Add built-in testing for misalignment handler
Add configurable built-in testing for the MN10300 misalignment handler.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00
David Howells
31ea24bba7 MN10300: Clean up the misalignment handler a little
Clean up the MN10300 misalignment handler a little by:

 (1) Use ilog2() rather than doing implementing log2() locally.

 (2) Make format_tbl[] const and static.

 (3) Making the debugging prints more consistent.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-11-12 10:41:17 -08:00