Version 1.0.0 did not add iv_offset to dun and did not mandate
sector size. This resulted in different on disk data format
compared to what version 2.1.0 will support. To support OTA upgrades with
legacy data format, adapt the sector size and iv_offset if legacy
encryption algorithm is used.
Change-Id: I3b7a0279bcb98c3cba9dec3f572c12d618fdc816
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Add support for legacy inline crypto mode in new v2 FBE
framework to make on disk data format compatible
to new v2 framework.
Change-Id: I3c1384604ee8e022db151299850b0dc330b6a17d
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
ICE address space was added to command queue address
space in eMMC JEDEC v5.2 spec so adapt the offset of
crypto registers accordingly.
Change-Id: I4740b2afa37d7dfb6ea0e4280b88dc0bdff9ca87
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
QTI implementation for block keyslot manager and
crypto vops for crypto support in CQHCI.
Change-Id: I9b64f85ca97c269a6ecd6fde2bb693745d4c43d4
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Wire up cqhci.c with the eMMC Crypto API and support for block layer inline
encryption additions and the keyslot manager.
Change-Id: I6860cd29d6f044f559385d438048b850faf9a8be
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Add functions to use eMMC inline encryption hardware capability
inline with JEDEC eMMC v5.2 specification and to work with
block keyslot manager. Also add crypto variant vops to handle
quirks in individual inline encryption hardware. The vops fallback
to default implementation which is JEDEC eMMC v5.2 compliant.
Change-Id: I72b85d572d7c76b966e34b80e7e8eca83a2bb35f
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Add crypto capability registers and structs defined in v5.2 of
JEDEC eMMC specification in prepration to add support for inline
encryption to eMMC controllers.
Change-Id: I8a42be348ca06cffbe841e590c4348990c9d7a08
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
To use block crypto based inline encryption mechanism
storage device driver should create a keyslot manager
and register it with device request queue. To achieve this
pass request queue pointer during host controller initialization
where request queue can be updated with keyslot manager.
Change-Id: I71f0005a1ad8867b6210e92878b8c112d436688e
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
Add QTI implementation for variant ops required for inline
encryption with wrapped key support. These include UFS
crypto ops and KSM ops. Also add crypto common library to cater
to different key programing mechanisms.
Change-Id: Ica930a8a806a78d4c2d074639cbed355b895a459
Signed-off-by: Gaurav Kashyap <gaurkash@codeaurora.org>
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
This brings fs/crypto and block/crypto support changes and fixes for new
FBE framework to work with inline encryption hardware. Also it enables
dm-default-key driver and wrapped key support changes for metadata encryption.
Conflicts:
block/blk-merge.c
drivers/scsi/ufs/ufshcd.h
fs/ext4/inode.c
Change-Id: Id9349c76c5deb6dabc365bc85d0431ac6c0966fe
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Signed-off-by: Blagovest Kolenichev <bkolenichev@codeaurora.org>
Avoid any host driver ops access after register driver gets killed
by marking it as NULL.
Change-Id: Idd268d5d8d31569c4272fde566866c4d79bc1cad
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Add code to pick hang data offset based on deviceID.
Change-Id: I865fc90ea558d2626672b51c5cecadfdf93358b3
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
The coresight driver is freeing up d_req as part of notify
from write_complete. Accessing write_done form qdss_close,
wait_for_completion will be stuck there causing watchdog
bark.
Fix this by making f_qdss independent of coresight & bridge
driver from initializing complete. Initialization of
completion now occurs from alloc_req.
Change-Id: Ie6b1cd445ed6bb38c1a555f6c4c41068090e4fac
Signed-off-by: Udipto Goswami <ugoswami@codeaurora.org>
When shared_ee dtsi flag is set then don't depend on the
shared_se checks in prepare/unprepare transfer
hardware and runtime resume/suspend APIs of spi driver. Also
use runtime resume/suspend calls from prepare/unprepare
message so that dual EE use case for spi will not be effected.
This change is to help in the cases where spi can be used
from secure and non-secure use cases. Spi framework
calls unprepare transfer hardware from a kthread after the
spi_pump_message call is completed and by that time spi driver
might be getting used from a secure use case and at the same time
unprepare transfer hardware is selecting the pinctrl to sleep state.
Change-Id: Ic8ea126ca5cddd3ca45c080a39841dd6ec1f6760
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Removing the APIs related to ctrl_read since those are
not used by any client of f_qdss.
Change-Id: Idf7f1ffd8afe8a72f83e036a7986d35f2f71bea8
Signed-off-by: Udipto Goswami <ugoswami@codeaurora.org>
Extend support to configure diag over STM using HW ACCEL command
for APPS.
Change-Id: Ifd9bf9867e910e9df4e1b6bddd94012c82f2be4f
Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
Update the max current limit configuration as per the
hardware capability.
- max-lim for master only config - 5A
- max-ilim for master and slave config - 10A
While at it, update the min-ilim setting to 750mA as per
the hardware recommendation.
Change-Id: I08793aafd0b416a597c3b51afff4ef624129f731
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
The need for the core to be brought out of low power mode
and put it back in low power mode during the boot up
to ensure that the core is in a proper known state is
interfering with the charger detection sequence of the
HS PHY.
Normally on platforms where the PMIC charger does the
charger detection this was prevented with the dpdm
regulator is_enabled check. But on platforms where the
USB HS PHY does the charger detection, the PMIC does not
enable the DPDM regulator, so the glue driver goes ahead
and put the core in known low power state.
Fix this by setting the dpdm_enable to true when the
charger detection sequence is started and clear the
dpdm_enable and notify the DISABLE_EVENT to glue driver
after the charger detection is done.
Change-Id: Ic7e2ec54b483b925797a72270831808fcb2c8bcd
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Add atos self test to perform atos for different sids. To enable,
set CONFIG_ARM_SMMU_SELFTEST and arm_smmu.selftest=1 and set the
sids and masks in arm_smmu.selftestsids in the below format
smmu_name,no_of_sids,sid:mask.
for eg: arm_smmu.selftestsids=kgsl,0x1,0x7:0x400,apps,0x2,
0x1:0x0,0x51f:0x0
Change-Id: I74134ed712e06a17b1570256e2ee3820df2f4457
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Define isp hw and isp hw pix path feature ids. This feature
information used for some target skus to check the particular
isp hw instance supported or not during the probe time.
Define feature type disable or enable. Some features are enable
type, If bit is set in the fuse register means feature is enabled.
Some features are disabled type, If bit is set in the fuse
register means feature is disabled.
Change-Id: Ib1c4df6326859ba9b5c8700337a9b9a24b300fb1
Signed-off-by: Ravikishore Pampana <rpampana@codeaurora.org>
If all the cpu's in a cluster are offline, pmu events are not
getting created for offline/inactive cluster. As the counter
registers are memory mapped, pmu event enable/read for
offline/inactive cluster, should be allowed from an online
cpu in online/active cluster. Once a cpu comes back online
from offline/inactive cluster, migrate cluster pmu events.
Change-Id: I653b15f44ecf98be54da272c350e28e769c0a24e
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Add socinfo support for SDM660 SoC and update the
bindings for the same.
Change-Id: Ieed54fda37e88192809b0d63da049802538c1997
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
