77ef50a522
This patch is the result of an automatic script that consolidates the format of all the headers in include/asm-x86/. The format: 1. No leading underscore. Names with leading underscores are reserved. 2. Pathname components are separated by two underscores. So we can distinguish between mm_types.h and mm/types.h. 3. Everything except letters and numbers are turned into single underscores. Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com>
125 lines
3.5 KiB
C
125 lines
3.5 KiB
C
#ifndef ASM_X86__VISWS__COBALT_H
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#define ASM_X86__VISWS__COBALT_H
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#include <asm/fixmap.h>
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/*
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* Cobalt SGI Visual Workstation system ASIC
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*/
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#define CO_CPU_NUM_PHYS 0x1e00
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#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
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#define CO_CPU_MAX 4
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#define CO_CPU_PHYS 0xc2000000
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#define CO_APIC_PHYS 0xc4000000
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/* see set_fixmap() and asm/fixmap.h */
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#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU))
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#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC))
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/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
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#define CO_CPU_REV 0x08
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#define CO_CPU_CTRL 0x10
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#define CO_CPU_STAT 0x20
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#define CO_CPU_TIMEVAL 0x30
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/* CO_CPU_CTRL bits */
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#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */
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#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */
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/* CO_CPU_STATUS bits */
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#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */
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/* CO_CPU_TIMEVAL value */
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#define CO_TIME_HZ 100000000 /* Cobalt core rate */
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/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
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#define CO_APIC_HI(n) (((n) * 0x10) + 4)
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#define CO_APIC_LO(n) ((n) * 0x10)
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#define CO_APIC_ID 0x0ffc
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/* CO_APIC_ID bits */
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#define CO_APIC_ENABLE 0x00000100
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/* CO_APIC_LO bits */
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#define CO_APIC_MASK 0x00010000 /* 0 = enabled */
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#define CO_APIC_LEVEL 0x00008000 /* 0 = edge */
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/*
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* Where things are physically wired to Cobalt
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* #defines with no board _<type>_<rev>_ are common to all (thus far)
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*/
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#define CO_APIC_IDE0 4
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#define CO_APIC_IDE1 2 /* Only on 320 */
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#define CO_APIC_8259 12 /* serial, floppy, par-l-l */
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/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
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#define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */
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#define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */
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#define CO_APIC_PIIX4_USB 7 /* this one is weird */
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/* Lithium PCI Bridge B -- "the one with PIIX4" */
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#define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */
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#define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */
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#define CO_APIC_VIDOUT0 16
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#define CO_APIC_VIDOUT1 17
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#define CO_APIC_VIDIN0 18
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#define CO_APIC_VIDIN1 19
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#define CO_APIC_LI_AUDIO 22
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#define CO_APIC_AS 24
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#define CO_APIC_RE 25
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#define CO_APIC_CPU 28 /* Timer and Cache interrupt */
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#define CO_APIC_NMI 29
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#define CO_APIC_LAST CO_APIC_NMI
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/*
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* This is how irqs are assigned on the Visual Workstation.
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* Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
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* All other devices (including PCI) go to Cobalt and are irq's 16 on up.
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*/
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#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */
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#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
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#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
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#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */
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#define CO_IRQ_IDE0 14 /* knowledge of... */
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#define CO_IRQ_IDE1 15 /* ... ide driver defaults! */
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#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259)
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#ifdef CONFIG_X86_VISWS_APIC
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static inline void co_cpu_write(unsigned long reg, unsigned long v)
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{
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*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
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}
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static inline unsigned long co_cpu_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
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}
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static inline void co_apic_write(unsigned long reg, unsigned long v)
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{
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*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
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}
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static inline unsigned long co_apic_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
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}
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#endif
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extern char visws_board_type;
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#define VISWS_320 0
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#define VISWS_540 1
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extern char visws_board_rev;
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#endif /* ASM_X86__VISWS__COBALT_H */
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