Dinh Nguyen 0691bb1b5a clk: socfpga: add divider registers to the main pll outputs ... The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>		2014-05-12 12:27:22 -05:00
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clk-gate.c	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
clk-periph.c	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
clk-pll.c	clk: socfpga: Support multiple parents for the pll clocks	2014-02-26 12:23:40 -08:00
clk.c	clk: socfpga: Fix section mismatch warning	2014-03-18 23:42:35 -07:00
clk.h	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
Makefile	clk: socfpga: split clk code	2014-02-18 14:08:13 -08:00