56ae583330
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <asm/gt64120.h>
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#include <asm/mach-cobalt/cobalt.h>
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/*
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* Device 31 on the GT64111 is used to generate PCI special
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* cycles, so we shouldn't expected to find a device there ...
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*/
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static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
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{
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if (bus->number == 0 && PCI_SLOT(devfn) < 31)
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return 0;
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return -1;
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}
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static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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if (pci_range_ck(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 4:
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PCI_CFG_SET(devfn, where);
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*val = GT_READ(GT_PCI0_CFGDATA_OFS);
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return PCIBIOS_SUCCESSFUL;
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case 2:
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PCI_CFG_SET(devfn, (where & ~0x3));
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*val = GT_READ(GT_PCI0_CFGDATA_OFS)
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>> ((where & 3) * 8);
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return PCIBIOS_SUCCESSFUL;
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case 1:
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PCI_CFG_SET(devfn, (where & ~0x3));
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*val = GT_READ(GT_PCI0_CFGDATA_OFS)
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>> ((where & 3) * 8);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 tmp;
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if (pci_range_ck(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 4:
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PCI_CFG_SET(devfn, where);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
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return PCIBIOS_SUCCESSFUL;
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case 2:
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PCI_CFG_SET(devfn, (where & ~0x3));
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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tmp &= ~(0xffff << ((where & 0x3) * 8));
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tmp |= (val << ((where & 0x3) * 8));
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GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
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return PCIBIOS_SUCCESSFUL;
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case 1:
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PCI_CFG_SET(devfn, (where & ~0x3));
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tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
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tmp &= ~(0xff << ((where & 0x3) * 8));
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tmp |= (val << ((where & 0x3) * 8));
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GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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struct pci_ops gt64111_pci_ops = {
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.read = gt64111_pci_read_config,
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.write = gt64111_pci_write_config,
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};
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