7b5dea1234
Wakeup sources on PXA3 are enabled at two levels. First, the MFP configuration has to be set to enable which edges a specific pin will trigger a wakeup. The pin also has to be routed to a functional unit. Lastly, the functional unit must be enabled as a wakeup source in the appropriate AD*ER registers (AD2D0ER for standby resume.) This doesn't fit well with the IRQ wake scheme - we currently do a best effort conversion from IRQ numbers to functional unit wake enable bits. For instance, there's several USB client related enable bits but there's no corresponding IRQs to determine which you'd want. Conversely, there's a single enable bit covering several functional units. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
114 lines
2.6 KiB
ArmAsm
114 lines
2.6 KiB
ArmAsm
/*
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* PXA27x standby mode
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*
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* Author: David Burrage
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa-regs.h>
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.text
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#ifdef CONFIG_PXA27x
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ENTRY(pxa_cpu_standby)
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ldr r0, =PSSR
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mov r1, #(PSSR_PH | PSSR_STS)
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mov r2, #PWRMODE_STANDBY
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mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
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ldr ip, [r3]
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b 1f
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.align 5
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1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
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str r1, [r0] @ make sure PSSR_PH/STS are clear
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mov pc, lr
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#endif
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#ifdef CONFIG_PXA3xx
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#define MDCNFG 0x0000
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#define MDCNFG_DMCEN (1 << 30)
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#define DDR_HCAL 0x0060
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#define DDR_HCAL_HCRNG 0x1f
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#define DDR_HCAL_HCPROG (1 << 28)
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#define DDR_HCAL_HCEN (1 << 31)
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#define DMCIER 0x0070
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#define DMCIER_EDLP (1 << 29)
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#define DMCISR 0x0078
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#define RCOMP 0x0100
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#define RCOMP_SWEVAL (1 << 31)
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ENTRY(pm_enter_standby_start)
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mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG)
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add r1, r1, #0x00100000
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/*
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* Preload the TLB entry for accessing the dynamic memory
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* controller registers. Note that page table lookups will
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* fail until the dynamic memory controller has been
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* reinitialised - and that includes MMU page table walks.
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* This also means that only the dynamic memory controller
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* can be reliably accessed in the code following standby.
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*/
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ldr r2, [r1] @ Dummy read MDCNFG
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mcr p14, 0, r0, c7, c0, 0
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.rept 8
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nop
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.endr
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ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN
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bic r0, r0, #DDR_HCAL_HCEN
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str r0, [r1, #DDR_HCAL]
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1: ldr r0, [r1, #DDR_HCAL]
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tst r0, #DDR_HCAL_HCEN
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bne 1b
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ldr r0, [r1, #RCOMP] @ Initiate RCOMP
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orr r0, r0, #RCOMP_SWEVAL
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str r0, [r1, #RCOMP]
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mov r0, #~0 @ Clear interrupts
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str r0, [r1, #DMCISR]
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ldr r0, [r1, #DMCIER] @ set DMIER[EDLP]
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orr r0, r0, #DMCIER_EDLP
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str r0, [r1, #DMCIER]
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ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
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bic r0, r0, #DDR_HCAL_HCRNG
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orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
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str r0, [r1, #DDR_HCAL]
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1: ldr r0, [r1, #DMCISR]
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tst r0, #DMCIER_EDLP
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beq 1b
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ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN]
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orr r0, r0, #MDCNFG_DMCEN
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str r0, [r1, #MDCNFG]
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1: ldr r0, [r1, #MDCNFG]
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tst r0, #MDCNFG_DMCEN
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beq 1b
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ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG]
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orr r0, r0, #2 @ HCRNG
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str r0, [r1, #DDR_HCAL]
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ldr r0, [r1, #DMCIER] @ Clear the interrupt
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bic r0, r0, #0x20000000
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str r0, [r1, #DMCIER]
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mov pc, lr
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ENTRY(pm_enter_standby_end)
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#endif
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