445959821f
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
88 lines
2.1 KiB
ArmAsm
88 lines
2.1 KiB
ArmAsm
/*
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* include/asm-arm/arch-omap/entry-macro.S
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*
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* Low-level IRQ helper macros for OMAP-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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#if defined(CONFIG_ARCH_OMAP1)
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#if defined(CONFIG_ARCH_OMAP730) && \
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(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
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#error "FIXME: OMAP730 doesn't support multiple-OMAP"
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#elif defined(CONFIG_ARCH_OMAP730)
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#define INT_IH2_IRQ INT_730_IH2_IRQ
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#elif defined(CONFIG_ARCH_OMAP15XX)
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#define INT_IH2_IRQ INT_1510_IH2_IRQ
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#elif defined(CONFIG_ARCH_OMAP16XX)
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#define INT_IH2_IRQ INT_1610_IH2_IRQ
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#else
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#warning "IH2 IRQ defaulted"
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#define INT_IH2_IRQ INT_1510_IH2_IRQ
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#endif
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
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ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
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ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
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mov \irqstat, #0xffffffff
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bic \tmp, \irqstat, \tmp
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tst \irqnr, \tmp
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beq 1510f
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ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
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cmp \irqnr, #0
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ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
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cmpeq \irqnr, #INT_IH2_IRQ
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ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
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ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
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addeqs \irqnr, \irqnr, #32
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1510:
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.endm
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#elif defined(CONFIG_ARCH_OMAP24XX)
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#include <asm/arch/omap24xx.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =OMAP2_VA_IC_BASE
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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2222:
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ldrne \irqnr, [\base, #IRQ_SIR_IRQ]
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.endm
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.macro irq_prio_table
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.endm
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#endif
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