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android_kernel_motorola_sm6225/arch/powerpc/boot/dts/mpc8548cds.dts
Kumar Gala 1b3c5cdab4 [POWERPC] Move PCI nodes to be sibilings with SOC nodes 
Updated the device trees to have the PCI nodes be at the same level as
the SOC node.  This is to make it so that the SOC nodes children address
space is just on chip registers and not other bus memory as well.

Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge
that exists in the PHB.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-14 08:53:22 -05:00

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/*
* MPC8548 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "MPC8548CDS";
compatible = "MPC8548CDS", "MPC85xxCDS";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
};
};
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <25000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
/* eTSEC 3/4 are currently broken
ethernet@26000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <26000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
ethernet@27000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <27000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
*/
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci@e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
02000 0 0 2 &mpic 1 1
02000 0 0 3 &mpic 2 1
02000 0 0 4 &mpic 3 1
/* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1
02800 0 0 2 &mpic 2 1
02800 0 0 3 &mpic 3 1
02800 0 0 4 &mpic 0 1
/* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1
03000 0 0 2 &mpic 3 1
03000 0 0 3 &mpic 0 1
03000 0 0 4 &mpic 1 1
/* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1
04000 0 0 2 &mpic 1 1
04000 0 0 3 &mpic 2 1
04000 0 0 4 &mpic 3 1
/* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1
06000 0 0 2 &mpic 1 1
06000 0 0 3 &mpic 2 1
06000 0 0 4 &mpic 3 1
/* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1
0a000 0 0 2 &mpic 1 1
0a000 0 0 3 &mpic 2 1
0a000 0 0 4 &mpic 3 1
/* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1
0a800 0 0 2 &mpic 2 1
0a800 0 0 3 &mpic 3 1
0a800 0 0 4 &mpic 0 1
/* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1
0b000 0 0 2 &mpic 3 1
0b000 0 0 3 &mpic 0 1
0b000 0 0 4 &mpic 1 1
/* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1
0c000 0 0 2 &mpic 1 1
0c000 0 0 3 &mpic 2 1
0c000 0 0 4 &mpic 3 1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
/* IDSEL 0x04 (VIA chip) */
2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
};
};
};
pci@e0009000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
pcie@e000a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 08000000>;
};
};
};
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