12f0e670ff
Daniel writes: New pull for -next. Highlights: - rc6/turbo support for hsw (Eugeni) - improve corner-case of the reset handling code - gpu reset handling should be rock-solid now - support for fb offset > 4096 pixels on gen4+ (yeah, you need some fairly big screens to hit that) - the "Flush Me Harder" patch to fix the gen6+ fallout from disabling the flushing_list - no more /dev/agpgart on gen6+! - HAS_PCH_xxx improvements from Paulo - a few minor bits&pieces all over, most of it in thew hsw code * tag 'drm-intel-next-2012-07-06' of git://people.freedesktop.org/~danvet/drm-intel: (40 commits) drm/i915: program FDI_RX TP and FDI delays drm/i915: introduce for_each_encoder_on_crtc drm/i915: adjust framebuffer base address on gen4+ drm/i915: introduce crtc->dspaddr_offset drm/i915: Reject page flips with changed format/offset/pitch drm/i915: Zero initialize mode_cmd drm/i915: don't return a spurious -EIO from intel_ring_begin drm/i915: properly SIGBUS on I/O errors drm/i915: don't hang userspace when the gpu reset is stuck drm/i915: non-interruptible sleeps can't handle -EAGAIN drm/i915: don't trylock in the gpu reset code drm/i915: fix PIPE_DDI_PORT_MASK drm/i915: prevent bogus intel_update_fbc notifications drm/i915: re-initialize DDI buffer translations after resume drm/i915: don't ironlake_init_pch_refclk() on LPT drm/i915: get rid of dev_priv->info->has_pch_split drm/i915: add PCH_NONE to enum intel_pch drm/i915: prefer wide & slow to fast & narrow in DP configs drm/i915: fix up ilk rc6 disabling confusion drm/i915: move force wake support into intel_pm ... |
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