ffadcc2ff4
When changing power states from D0->DX and then from DX->D0, some Intel PCIE chipsets will cause a device reset to occur. This will cause problems for any D State other than D3, since any state information that the driver will expect to be present coming from a D1 or D2 state will have been cleared. This patch addes a flag to the pci_dev structure to indicate that devices should not use states D1 or D2, and will set that flag for the affected chipsets. This patch also modifies pci_set_power_state() so that when a device driver tries to set the power state on a device that is downstream from an affected chipset, or on one of the affected devices it only allows state changes to or from D0 & D3. In addition, this patch allows the delay time between D3->D0 to be changed via a quirk. These chipsets also need additional time to change states beyond the normal 10ms. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
996 lines
26 KiB
C
996 lines
26 KiB
C
/*
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* $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
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*
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* PCI Bus Services, see include/linux/pci.h for further explanation.
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*
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
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*
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* Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <asm/dma.h> /* isa_dma_bridge_buggy */
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#include "pci.h"
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unsigned int pci_pm_d3_delay = 10;
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/**
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* pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
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* @bus: pointer to PCI bus structure to search
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*
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* Given a PCI bus, returns the highest PCI bus number present in the set
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* including the given PCI bus and its list of child PCI buses.
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*/
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unsigned char __devinit
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pci_bus_max_busnr(struct pci_bus* bus)
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{
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struct list_head *tmp;
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unsigned char max, n;
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max = bus->subordinate;
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list_for_each(tmp, &bus->children) {
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n = pci_bus_max_busnr(pci_bus_b(tmp));
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if(n > max)
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max = n;
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}
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return max;
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}
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EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
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#if 0
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/**
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* pci_max_busnr - returns maximum PCI bus number
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*
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* Returns the highest PCI bus number present in the system global list of
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* PCI buses.
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*/
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unsigned char __devinit
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pci_max_busnr(void)
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{
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struct pci_bus *bus = NULL;
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unsigned char max, n;
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max = 0;
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while ((bus = pci_find_next_bus(bus)) != NULL) {
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n = pci_bus_max_busnr(bus);
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if(n > max)
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max = n;
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}
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return max;
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}
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#endif /* 0 */
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static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
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{
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u8 id;
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int ttl = 48;
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while (ttl--) {
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pci_bus_read_config_byte(bus, devfn, pos, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
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&id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
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{
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return __pci_find_next_cap(dev->bus, dev->devfn,
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pos + PCI_CAP_LIST_NEXT, cap);
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}
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EXPORT_SYMBOL_GPL(pci_find_next_capability);
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static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
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{
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u16 status;
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u8 pos;
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pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pos = PCI_CAPABILITY_LIST;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pos = PCI_CB_CAPABILITY_LIST;
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break;
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default:
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return 0;
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}
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return __pci_find_next_cap(bus, devfn, pos, cap);
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_PCIX PCI-X
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* %PCI_CAP_ID_EXP PCI Express
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*/
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
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}
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/**
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* pci_bus_find_capability - query for devices' capabilities
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* @bus: the PCI bus to query
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* @devfn: PCI device to query
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* @cap: capability code
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*
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* Like pci_find_capability() but works for pci devices that do not have a
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* pci_dev structure set up yet.
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*
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it.
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*/
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int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
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{
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u8 hdr_type;
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pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
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return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
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}
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/**
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* pci_find_ext_capability - Find an extended capability
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Returns the address of the requested extended capability structure
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* within the device's PCI configuration space or 0 if the device does
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* not support it. Possible values for @cap:
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*
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* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
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* %PCI_EXT_CAP_ID_VC Virtual Channel
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* %PCI_EXT_CAP_ID_DSN Device Serial Number
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* %PCI_EXT_CAP_ID_PWR Power Budgeting
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*/
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int pci_find_ext_capability(struct pci_dev *dev, int cap)
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{
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u32 header;
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int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
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int pos = 0x100;
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if (dev->cfg_size <= 256)
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return 0;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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return 0;
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < 0x100)
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break;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_find_ext_capability);
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/**
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* pci_find_parent_resource - return resource region of parent bus of given region
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* @dev: PCI device structure contains resources to be searched
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* @res: child resource record for which parent is sought
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*
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* For given resource region of given device, return the resource
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* region of parent bus the given region is contained in or where
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* it should be allocated from.
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*/
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struct resource *
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pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
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{
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const struct pci_bus *bus = dev->bus;
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int i;
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struct resource *best = NULL;
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for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
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struct resource *r = bus->resource[i];
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if (!r)
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continue;
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if (res->start && !(res->start >= r->start && res->end <= r->end))
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continue; /* Not contained */
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if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
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continue; /* Wrong type */
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if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
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return r; /* Exact match */
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if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
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best = r; /* Approximating prefetchable by non-prefetchable */
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}
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return best;
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}
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/**
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* pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
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* @dev: PCI device to have its BARs restored
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*
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* Restore the BAR values for a given device, so as to make it
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* accessible by its driver.
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*/
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void
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pci_restore_bars(struct pci_dev *dev)
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{
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int i, numres;
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switch (dev->hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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numres = 6;
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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numres = 2;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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numres = 1;
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break;
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default:
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/* Should never get here, but just in case... */
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return;
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}
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for (i = 0; i < numres; i ++)
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pci_update_resource(dev, &dev->resource[i], i);
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}
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int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
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/**
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* pci_set_power_state - Set the power state of a PCI device
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* @dev: PCI device to be suspended
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* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
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*
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* Transition a device to a new power state, using the Power Management
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* Capabilities in the device's config space.
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*
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* RETURN VALUE:
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* -EINVAL if trying to enter a lower state than we're already in.
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* 0 if we're already in the requested state.
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* -EIO if device does not support PCI PM.
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* 0 if we can successfully change the power state.
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*/
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int
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pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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int pm, need_restore = 0;
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u16 pmcsr, pmc;
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/* bound the state we're entering */
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if (state > PCI_D3hot)
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state = PCI_D3hot;
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/* Validate current state:
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* Can enter D0 from any state, but if we can only go deeper
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* to sleep if we're already in a low power state
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*/
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if (state != PCI_D0 && dev->current_state > state) {
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printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
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__FUNCTION__, pci_name(dev), state, dev->current_state);
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return -EINVAL;
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} else if (dev->current_state == state)
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return 0; /* we're already there */
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/*
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* If the device or the parent bridge can't support PCI PM, ignore
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* the request if we're doing anything besides putting it into D0
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* (which would only happen on boot).
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*/
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if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
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return 0;
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/* find PCI PM capability in list */
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pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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/* abort if the device doesn't support PM capabilities */
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if (!pm)
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return -EIO;
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pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
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if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
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printk(KERN_DEBUG
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"PCI: %s has unsupported PM cap regs version (%u)\n",
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pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
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return -EIO;
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}
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/* check if this device supports the desired state */
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if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
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return -EIO;
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else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
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return -EIO;
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pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
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/* If we're (effectively) in D3, force entire word to 0.
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* This doesn't affect PME_Status, disables PME_En, and
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* sets PowerState to 0.
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*/
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switch (dev->current_state) {
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case PCI_D0:
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case PCI_D1:
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case PCI_D2:
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pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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pmcsr |= state;
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break;
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case PCI_UNKNOWN: /* Boot-up */
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if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
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&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
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need_restore = 1;
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/* Fall-through: force to D0 */
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default:
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pmcsr = 0;
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break;
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}
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/* enter specified state */
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pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
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/* Mandatory power management transition delays */
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/* see PCI PM 1.1 5.6.1 table 18 */
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if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
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msleep(pci_pm_d3_delay);
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else if (state == PCI_D2 || dev->current_state == PCI_D2)
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udelay(200);
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/*
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* Give firmware a chance to be called, such as ACPI _PRx, _PSx
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* Firmware method after native method ?
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*/
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if (platform_pci_set_power_state)
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platform_pci_set_power_state(dev, state);
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dev->current_state = state;
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/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
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* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
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* from D3hot to D0 _may_ perform an internal reset, thereby
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* going to "D0 Uninitialized" rather than "D0 Initialized".
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* For example, at least some versions of the 3c905B and the
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* 3c556B exhibit this behaviour.
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*
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* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
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* devices in a D3hot state at boot. Consequently, we need to
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* restore at least the BARs so that the device will be
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* accessible to its driver.
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*/
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if (need_restore)
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pci_restore_bars(dev);
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return 0;
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}
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int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
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/**
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* pci_choose_state - Choose the power state of a PCI device
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* @dev: PCI device to be suspended
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* @state: target sleep state for the whole system. This is the value
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* that is passed to suspend() function.
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*
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* Returns PCI power state suitable for given device and given system
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* message.
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*/
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pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
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{
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int ret;
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if (!pci_find_capability(dev, PCI_CAP_ID_PM))
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return PCI_D0;
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if (platform_pci_choose_state) {
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ret = platform_pci_choose_state(dev, state);
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if (ret >= 0)
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state.event = ret;
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}
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switch (state.event) {
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case PM_EVENT_ON:
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return PCI_D0;
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case PM_EVENT_FREEZE:
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case PM_EVENT_SUSPEND:
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return PCI_D3hot;
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default:
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printk("They asked me for state %d\n", state.event);
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BUG();
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}
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return PCI_D0;
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}
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EXPORT_SYMBOL(pci_choose_state);
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/**
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* pci_save_state - save the PCI configuration space of a device before suspending
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* @dev: - PCI device that we're dealing with
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*/
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int
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pci_save_state(struct pci_dev *dev)
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{
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int i;
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/* XXX: 100% dword access ok here? */
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for (i = 0; i < 16; i++)
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pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
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if ((i = pci_save_msi_state(dev)) != 0)
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return i;
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if ((i = pci_save_msix_state(dev)) != 0)
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return i;
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return 0;
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}
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/**
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* pci_restore_state - Restore the saved state of a PCI device
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* @dev: - PCI device that we're dealing with
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*/
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int
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pci_restore_state(struct pci_dev *dev)
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{
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int i;
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int val;
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/*
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* The Base Address register should be programmed before the command
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* register(s)
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*/
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for (i = 15; i >= 0; i--) {
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pci_read_config_dword(dev, i * 4, &val);
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if (val != dev->saved_config_space[i]) {
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printk(KERN_DEBUG "PM: Writing back config space on "
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"device %s at offset %x (was %x, writing %x)\n",
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pci_name(dev), i,
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val, (int)dev->saved_config_space[i]);
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pci_write_config_dword(dev,i * 4,
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dev->saved_config_space[i]);
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}
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}
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pci_restore_msi_state(dev);
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pci_restore_msix_state(dev);
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return 0;
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}
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/**
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* pci_enable_device_bars - Initialize some of a device for use
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* @dev: PCI device to be initialized
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* @bars: bitmask of BAR's that must be configured
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*
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
* to enable selected I/O and memory resources. Wake up the device if it
|
|
* was suspended. Beware, this function can fail.
|
|
*/
|
|
|
|
int
|
|
pci_enable_device_bars(struct pci_dev *dev, int bars)
|
|
{
|
|
int err;
|
|
|
|
err = pci_set_power_state(dev, PCI_D0);
|
|
if (err < 0 && err != -EIO)
|
|
return err;
|
|
err = pcibios_enable_device(dev, bars);
|
|
if (err < 0)
|
|
return err;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_device - Initialize device before it's used by a driver.
|
|
* @dev: PCI device to be initialized
|
|
*
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
* to enable I/O and memory. Wake up the device if it was suspended.
|
|
* Beware, this function can fail.
|
|
*/
|
|
int
|
|
pci_enable_device(struct pci_dev *dev)
|
|
{
|
|
int err;
|
|
|
|
if (dev->is_enabled)
|
|
return 0;
|
|
|
|
err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
|
|
if (err)
|
|
return err;
|
|
pci_fixup_device(pci_fixup_enable, dev);
|
|
dev->is_enabled = 1;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcibios_disable_device - disable arch specific PCI resources for device dev
|
|
* @dev: the PCI device to disable
|
|
*
|
|
* Disables architecture specific PCI resources for the device. This
|
|
* is the default implementation. Architecture implementations can
|
|
* override this.
|
|
*/
|
|
void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
|
|
|
|
/**
|
|
* pci_disable_device - Disable PCI device after use
|
|
* @dev: PCI device to be disabled
|
|
*
|
|
* Signal to the system that the PCI device is not in use by the system
|
|
* anymore. This only involves disabling PCI bus-mastering, if active.
|
|
*/
|
|
void
|
|
pci_disable_device(struct pci_dev *dev)
|
|
{
|
|
u16 pci_command;
|
|
|
|
if (dev->msi_enabled)
|
|
disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
|
|
PCI_CAP_ID_MSI);
|
|
if (dev->msix_enabled)
|
|
disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
|
|
PCI_CAP_ID_MSIX);
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &pci_command);
|
|
if (pci_command & PCI_COMMAND_MASTER) {
|
|
pci_command &= ~PCI_COMMAND_MASTER;
|
|
pci_write_config_word(dev, PCI_COMMAND, pci_command);
|
|
}
|
|
dev->is_busmaster = 0;
|
|
|
|
pcibios_disable_device(dev);
|
|
dev->is_enabled = 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_wake - enable device to generate PME# when suspended
|
|
* @dev: - PCI device to operate on
|
|
* @state: - Current state of device.
|
|
* @enable: - Flag to enable or disable generation
|
|
*
|
|
* Set the bits in the device's PM Capabilities to generate PME# when
|
|
* the system is suspended.
|
|
*
|
|
* -EIO is returned if device doesn't have PM Capabilities.
|
|
* -EINVAL is returned if device supports it, but can't generate wake events.
|
|
* 0 if operation is successful.
|
|
*
|
|
*/
|
|
int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
|
|
{
|
|
int pm;
|
|
u16 value;
|
|
|
|
/* find PCI PM capability in list */
|
|
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
|
|
|
|
/* If device doesn't support PM Capabilities, but request is to disable
|
|
* wake events, it's a nop; otherwise fail */
|
|
if (!pm)
|
|
return enable ? -EIO : 0;
|
|
|
|
/* Check device's ability to generate PME# */
|
|
pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
|
|
|
|
value &= PCI_PM_CAP_PME_MASK;
|
|
value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
|
|
|
|
/* Check if it can generate PME# from requested state. */
|
|
if (!value || !(value & (1 << state)))
|
|
return enable ? -EINVAL : 0;
|
|
|
|
pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
|
|
|
|
/* Clear PME_Status by writing 1 to it and enable PME# */
|
|
value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
if (!enable)
|
|
value &= ~PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
|
|
{
|
|
u8 pin;
|
|
|
|
pin = dev->pin;
|
|
if (!pin)
|
|
return -1;
|
|
pin--;
|
|
while (dev->bus->self) {
|
|
pin = (pin + PCI_SLOT(dev->devfn)) % 4;
|
|
dev = dev->bus->self;
|
|
}
|
|
*bridge = dev;
|
|
return pin;
|
|
}
|
|
|
|
/**
|
|
* pci_release_region - Release a PCI bar
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_region
|
|
* @bar: BAR to release
|
|
*
|
|
* Releases the PCI I/O and memory resources previously reserved by a
|
|
* successful call to pci_request_region. Call this function only
|
|
* after all use of the PCI regions has ceased.
|
|
*/
|
|
void pci_release_region(struct pci_dev *pdev, int bar)
|
|
{
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
return;
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
|
|
release_region(pci_resource_start(pdev, bar),
|
|
pci_resource_len(pdev, bar));
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
|
|
release_mem_region(pci_resource_start(pdev, bar),
|
|
pci_resource_len(pdev, bar));
|
|
}
|
|
|
|
/**
|
|
* pci_request_region - Reserved PCI I/O and memory resource
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
* @bar: BAR to be reserved
|
|
* @res_name: Name to be associated with resource.
|
|
*
|
|
* Mark the PCI region associated with PCI device @pdev BR @bar as
|
|
* being reserved by owner @res_name. Do not access any
|
|
* address inside the PCI regions unless this call returns
|
|
* successfully.
|
|
*
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
* message is also printed on failure.
|
|
*/
|
|
int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
|
|
{
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
return 0;
|
|
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
|
|
if (!request_region(pci_resource_start(pdev, bar),
|
|
pci_resource_len(pdev, bar), res_name))
|
|
goto err_out;
|
|
}
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
|
|
if (!request_mem_region(pci_resource_start(pdev, bar),
|
|
pci_resource_len(pdev, bar), res_name))
|
|
goto err_out;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
|
|
"for device %s\n",
|
|
pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
|
|
bar + 1, /* PCI BAR # */
|
|
(unsigned long long)pci_resource_len(pdev, bar),
|
|
(unsigned long long)pci_resource_start(pdev, bar),
|
|
pci_name(pdev));
|
|
return -EBUSY;
|
|
}
|
|
|
|
|
|
/**
|
|
* pci_release_regions - Release reserved PCI I/O and memory resources
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_regions
|
|
*
|
|
* Releases all PCI I/O and memory resources previously reserved by a
|
|
* successful call to pci_request_regions. Call this function only
|
|
* after all use of the PCI regions has ceased.
|
|
*/
|
|
|
|
void pci_release_regions(struct pci_dev *pdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
pci_release_region(pdev, i);
|
|
}
|
|
|
|
/**
|
|
* pci_request_regions - Reserved PCI I/O and memory resources
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
* @res_name: Name to be associated with resource.
|
|
*
|
|
* Mark all PCI regions associated with PCI device @pdev as
|
|
* being reserved by owner @res_name. Do not access any
|
|
* address inside the PCI regions unless this call returns
|
|
* successfully.
|
|
*
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
* message is also printed on failure.
|
|
*/
|
|
int pci_request_regions(struct pci_dev *pdev, const char *res_name)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
if(pci_request_region(pdev, i, res_name))
|
|
goto err_out;
|
|
return 0;
|
|
|
|
err_out:
|
|
while(--i >= 0)
|
|
pci_release_region(pdev, i);
|
|
|
|
return -EBUSY;
|
|
}
|
|
|
|
/**
|
|
* pci_set_master - enables bus-mastering for device dev
|
|
* @dev: the PCI device to enable
|
|
*
|
|
* Enables bus-mastering on the device and calls pcibios_set_master()
|
|
* to do the needed arch specific settings.
|
|
*/
|
|
void
|
|
pci_set_master(struct pci_dev *dev)
|
|
{
|
|
u16 cmd;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
if (! (cmd & PCI_COMMAND_MASTER)) {
|
|
pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
|
|
cmd |= PCI_COMMAND_MASTER;
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
dev->is_busmaster = 1;
|
|
pcibios_set_master(dev);
|
|
}
|
|
|
|
#ifndef HAVE_ARCH_PCI_MWI
|
|
/* This can be overridden by arch code. */
|
|
u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
|
|
|
|
/**
|
|
* pci_generic_prep_mwi - helper function for pci_set_mwi
|
|
* @dev: the PCI device for which MWI is enabled
|
|
*
|
|
* Helper function for generic implementation of pcibios_prep_mwi
|
|
* function. Originally copied from drivers/net/acenic.c.
|
|
* Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
|
|
*
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
*/
|
|
static int
|
|
pci_generic_prep_mwi(struct pci_dev *dev)
|
|
{
|
|
u8 cacheline_size;
|
|
|
|
if (!pci_cache_line_size)
|
|
return -EINVAL; /* The system doesn't support MWI. */
|
|
|
|
/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
|
|
equal to or multiple of the right value. */
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
if (cacheline_size >= pci_cache_line_size &&
|
|
(cacheline_size % pci_cache_line_size) == 0)
|
|
return 0;
|
|
|
|
/* Write the correct value. */
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
|
|
/* Read it back. */
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
if (cacheline_size == pci_cache_line_size)
|
|
return 0;
|
|
|
|
printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
|
|
"by device %s\n", pci_cache_line_size << 2, pci_name(dev));
|
|
|
|
return -EINVAL;
|
|
}
|
|
#endif /* !HAVE_ARCH_PCI_MWI */
|
|
|
|
/**
|
|
* pci_set_mwi - enables memory-write-invalidate PCI transaction
|
|
* @dev: the PCI device for which MWI is enabled
|
|
*
|
|
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
|
|
* and then calls @pcibios_set_mwi to do the needed arch specific
|
|
* operations or a generic mwi-prep function.
|
|
*
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
*/
|
|
int
|
|
pci_set_mwi(struct pci_dev *dev)
|
|
{
|
|
int rc;
|
|
u16 cmd;
|
|
|
|
#ifdef HAVE_ARCH_PCI_MWI
|
|
rc = pcibios_prep_mwi(dev);
|
|
#else
|
|
rc = pci_generic_prep_mwi(dev);
|
|
#endif
|
|
|
|
if (rc)
|
|
return rc;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
if (! (cmd & PCI_COMMAND_INVALIDATE)) {
|
|
pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
|
|
cmd |= PCI_COMMAND_INVALIDATE;
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_clear_mwi - disables Memory-Write-Invalidate for device dev
|
|
* @dev: the PCI device to disable
|
|
*
|
|
* Disables PCI Memory-Write-Invalidate transaction on the device
|
|
*/
|
|
void
|
|
pci_clear_mwi(struct pci_dev *dev)
|
|
{
|
|
u16 cmd;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
if (cmd & PCI_COMMAND_INVALIDATE) {
|
|
cmd &= ~PCI_COMMAND_INVALIDATE;
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* pci_intx - enables/disables PCI INTx for device dev
|
|
* @pdev: the PCI device to operate on
|
|
* @enable: boolean: whether to enable or disable PCI INTx
|
|
*
|
|
* Enables/disables PCI INTx for device dev
|
|
*/
|
|
void
|
|
pci_intx(struct pci_dev *pdev, int enable)
|
|
{
|
|
u16 pci_command, new;
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
|
|
|
|
if (enable) {
|
|
new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
|
|
} else {
|
|
new = pci_command | PCI_COMMAND_INTX_DISABLE;
|
|
}
|
|
|
|
if (new != pci_command) {
|
|
pci_write_config_word(pdev, PCI_COMMAND, new);
|
|
}
|
|
}
|
|
|
|
#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
|
|
/*
|
|
* These can be overridden by arch-specific implementations
|
|
*/
|
|
int
|
|
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
|
|
{
|
|
if (!pci_dma_supported(dev, mask))
|
|
return -EIO;
|
|
|
|
dev->dma_mask = mask;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
|
|
{
|
|
if (!pci_dma_supported(dev, mask))
|
|
return -EIO;
|
|
|
|
dev->dev.coherent_dma_mask = mask;
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int __devinit pci_init(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
|
|
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
|
|
pci_fixup_device(pci_fixup_final, dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit pci_setup(char *str)
|
|
{
|
|
while (str) {
|
|
char *k = strchr(str, ',');
|
|
if (k)
|
|
*k++ = 0;
|
|
if (*str && (str = pcibios_setup(str)) && *str) {
|
|
if (!strcmp(str, "nomsi")) {
|
|
pci_no_msi();
|
|
} else {
|
|
printk(KERN_ERR "PCI: Unknown option `%s'\n",
|
|
str);
|
|
}
|
|
}
|
|
str = k;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
device_initcall(pci_init);
|
|
|
|
__setup("pci=", pci_setup);
|
|
|
|
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
|
|
/* FIXME: Some boxes have multiple ISA bridges! */
|
|
struct pci_dev *isa_bridge;
|
|
EXPORT_SYMBOL(isa_bridge);
|
|
#endif
|
|
|
|
EXPORT_SYMBOL_GPL(pci_restore_bars);
|
|
EXPORT_SYMBOL(pci_enable_device_bars);
|
|
EXPORT_SYMBOL(pci_enable_device);
|
|
EXPORT_SYMBOL(pci_disable_device);
|
|
EXPORT_SYMBOL(pci_find_capability);
|
|
EXPORT_SYMBOL(pci_bus_find_capability);
|
|
EXPORT_SYMBOL(pci_release_regions);
|
|
EXPORT_SYMBOL(pci_request_regions);
|
|
EXPORT_SYMBOL(pci_release_region);
|
|
EXPORT_SYMBOL(pci_request_region);
|
|
EXPORT_SYMBOL(pci_set_master);
|
|
EXPORT_SYMBOL(pci_set_mwi);
|
|
EXPORT_SYMBOL(pci_clear_mwi);
|
|
EXPORT_SYMBOL_GPL(pci_intx);
|
|
EXPORT_SYMBOL(pci_set_dma_mask);
|
|
EXPORT_SYMBOL(pci_set_consistent_dma_mask);
|
|
EXPORT_SYMBOL(pci_assign_resource);
|
|
EXPORT_SYMBOL(pci_find_parent_resource);
|
|
|
|
EXPORT_SYMBOL(pci_set_power_state);
|
|
EXPORT_SYMBOL(pci_save_state);
|
|
EXPORT_SYMBOL(pci_restore_state);
|
|
EXPORT_SYMBOL(pci_enable_wake);
|
|
|
|
/* Quirk info */
|
|
|
|
EXPORT_SYMBOL(isa_dma_bridge_buggy);
|
|
EXPORT_SYMBOL(pci_pci_problems);
|