android_kernel_motorola_sm6225/arch/openrisc
Peter Zijlstra 2191a85943 openrisc: Define memory barrier mb
[ Upstream commit 8b549c18ae81dbc36fb11e4aa08b8378c599ca95 ]

This came up in the discussion of the requirements of qspinlock on an
architecture.  OpenRISC uses qspinlock, but it was noticed that the
memmory barrier was not defined.

Peter defined it in the mail thread writing:

    As near as I can tell this should do. The arch spec only lists
    this one instruction and the text makes it sound like a completion
    barrier.

This is correct so applying this patch.

Signed-off-by: Peter Zijlstra <peterz@infradead.org>
[shorne@gmail.com:Turned the mail into a patch]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-06-03 08:38:10 +02:00
..
boot/dts DeviceTree for 4.15: 2017-11-14 18:25:40 -08:00
configs openrisc: add simple_smp dts and defconfig for simulators 2017-11-03 14:01:15 +09:00
include openrisc: Define memory barrier mb 2021-06-03 08:38:10 +02:00
kernel openrisc: Fix a memory leak 2021-05-26 11:48:31 +02:00
lib OpenRISC updates for v4.15 2017-11-13 12:12:00 -08:00
mm openrisc: Fix cache API compile issue when not inlining 2020-09-23 12:10:58 +02:00
Kconfig OpenRISC updates for 4.19 2018-08-23 14:09:37 -07:00
Kconfig.debug Kconfig: consolidate the "Kernel hacking" menu 2018-08-02 08:06:48 +09:00
Makefile kbuild: remove redundant LDFLAGS clearing in arch/*/Makefile 2018-07-19 08:40:27 +09:00