2cd0ebc83d
This patch fixes the TMU0 interrupt frequency on suspend/resume. During the resume the kernel reprograms the TMU0.ClockEvent mode but if the mode is periodic than the TMU0.TCOR is updated with a random wrong value without taking care latest valid saved value. There was no problem with No_HZ system where TMU0.TCOR isn't used. Signed-off-by: Francesco M. Virlinzi <francesco.virlinzi@st.com> Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
283 lines
6.5 KiB
C
283 lines
6.5 KiB
C
/*
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* arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
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*
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* Copyright (C) 2005 - 2007 Paul Mundt
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*
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* TMU handling code hacked out of arch/sh/kernel/time.c
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*
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* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
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* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2002, 2003, 2004 Paul Mundt
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* Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/seqlock.h>
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#include <linux/clockchips.h>
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#include <asm/timer.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/clock.h>
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#define TMU_TOCR_INIT 0x00
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#define TMU_TCR_INIT 0x0020
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#define TMU0 (0)
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#define TMU1 (1)
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static inline void _tmu_start(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_set_irq(int tmu_num, int enabled)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
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}
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static inline void _tmu_stop(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_clear_status(int tmu_num)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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/* Clear UNF bit */
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ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
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}
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static inline unsigned long _tmu_read(int tmu_num)
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{
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return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
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}
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static int tmu_timer_start(void)
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{
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_tmu_start(TMU0);
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_tmu_start(TMU1);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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static int tmu_timer_stop(void)
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{
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_tmu_stop(TMU0);
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_tmu_stop(TMU1);
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_tmu_clear_status(TMU0);
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return 0;
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}
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/*
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* also when the module_clk is scaled the TMU1
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* will show the same frequency
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*/
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static int tmus_are_scaled;
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static cycle_t tmu_timer_read(void)
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{
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return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
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}
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static unsigned long tmu_latest_interval[3];
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static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
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{
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unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
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unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
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_tmu_stop(tmu_num);
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ctrl_outl(interval, tmu_tcnt);
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tmu_latest_interval[tmu_num] = interval;
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/*
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* TCNT reloads from TCOR on underflow, clear it if we don't
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* intend to auto-reload
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*/
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ctrl_outl( reload ? interval : 0 , tmu_tcor);
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_tmu_start(tmu_num);
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}
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static int tmu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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static void tmu_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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ctrl_outl(0, TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device tmu0_clockevent = {
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.name = "tmu0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = tmu_set_mode,
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.set_next_event = tmu_set_next_event,
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};
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static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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{
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struct clock_event_device *evt = &tmu0_clockevent;
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_tmu_clear_status(TMU0);
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_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction tmu0_irq = {
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.name = "periodic/oneshot timer",
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.handler = tmu_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.mask = CPU_MASK_NONE,
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};
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static void __init tmu_clk_init(struct clk *clk)
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{
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u8 divisor = TMU_TCR_INIT & 0x7;
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int tmu_num = clk->name[3]-'0';
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ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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}
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static void tmu_clk_recalc(struct clk *clk)
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{
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int tmu_num = clk->name[3]-'0';
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unsigned long prev_rate = clk_get_rate(clk);
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unsigned long flags;
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u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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if(prev_rate==clk_get_rate(clk))
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return;
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if(tmu_num)
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return; /* No more work on TMU1 */
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local_irq_save(flags);
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tmus_are_scaled = (prev_rate > clk->rate);
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_tmu_stop(TMU0);
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tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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tmu0_clockevent.max_delta_ns =
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clockevent_delta2ns(-1, &tmu0_clockevent);
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tmu0_clockevent.min_delta_ns =
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clockevent_delta2ns(1, &tmu0_clockevent);
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if (tmus_are_scaled)
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tmu_latest_interval[TMU0] >>= 1;
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else
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tmu_latest_interval[TMU0] <<= 1;
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tmu_timer_set_interval(TMU0,
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tmu_latest_interval[TMU0],
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tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_start(TMU0);
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local_irq_restore(flags);
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}
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static struct clk_ops tmu_clk_ops = {
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.init = tmu_clk_init,
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.recalc = tmu_clk_recalc,
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};
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static struct clk tmu0_clk = {
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.name = "tmu0_clk",
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.ops = &tmu_clk_ops,
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};
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static struct clk tmu1_clk = {
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.name = "tmu1_clk",
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.ops = &tmu_clk_ops,
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};
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static int tmu_timer_init(void)
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{
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unsigned long interval;
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unsigned long frequency;
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setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
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tmu0_clk.parent = clk_get(NULL, "module_clk");
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tmu1_clk.parent = clk_get(NULL, "module_clk");
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tmu_timer_stop();
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
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!defined(CONFIG_CPU_SUBTYPE_SHX3)
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ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
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#endif
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clk_register(&tmu0_clk);
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clk_register(&tmu1_clk);
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clk_enable(&tmu0_clk);
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clk_enable(&tmu1_clk);
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frequency = clk_get_rate(&tmu0_clk);
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interval = (frequency + HZ / 2) / HZ;
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tmu_timer_set_interval(TMU0,interval, 1);
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tmu_timer_set_interval(TMU1,~0,1);
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_tmu_start(TMU1);
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sh_hpt_frequency = clk_get_rate(&tmu1_clk);
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tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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tmu0_clockevent.max_delta_ns =
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clockevent_delta2ns(-1, &tmu0_clockevent);
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tmu0_clockevent.min_delta_ns =
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clockevent_delta2ns(1, &tmu0_clockevent);
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tmu0_clockevent.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&tmu0_clockevent);
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return 0;
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}
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static struct sys_timer_ops tmu_timer_ops = {
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.init = tmu_timer_init,
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.start = tmu_timer_start,
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.stop = tmu_timer_stop,
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.read = tmu_timer_read,
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};
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struct sys_timer tmu_timer = {
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.name = "tmu",
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.ops = &tmu_timer_ops,
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};
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