97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
116 lines
3 KiB
C
116 lines
3 KiB
C
/*
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* IRQ vector handles
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/gt64120.h>
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#include <asm/mach-cobalt/cobalt.h>
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/*
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* We have two types of interrupts that we handle, ones that come in through
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* the CPU interrupt lines, and ones that come in on the via chip. The CPU
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* mappings are:
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*
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* 16 - Software interrupt 0 (unused) IE_SW0
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* 17 - Software interrupt 1 (unused) IE_SW1
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* 18 - Galileo chip (timer) IE_IRQ0
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* 19 - Tulip 0 + NCR SCSI IE_IRQ1
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* 20 - Tulip 1 IE_IRQ2
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* 21 - 16550 UART IE_IRQ3
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* 22 - VIA southbridge PIC IE_IRQ4
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* 23 - unused IE_IRQ5
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*
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* The VIA chip is a master/slave 8259 setup and has the following interrupts:
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*
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* 8 - RTC
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* 9 - PCI
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* 14 - IDE0
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* 15 - IDE1
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*/
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static inline void galileo_irq(void)
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{
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unsigned int mask, pending, devfn;
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mask = GT_READ(GT_INTRMASK_OFS);
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pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
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if (pending & GT_INTR_T0EXP_MSK) {
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GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
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do_IRQ(COBALT_GALILEO_IRQ);
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} else if (pending & GT_INTR_RETRYCTR0_MSK) {
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devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
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GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
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printk(KERN_WARNING
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"Galileo: PCI retry count exceeded (%02x.%u)\n",
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PCI_SLOT(devfn), PCI_FUNC(devfn));
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} else {
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GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
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printk(KERN_WARNING
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"Galileo: masking unexpected interrupt %08x\n", pending);
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}
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}
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static inline void via_pic_irq(void)
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{
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int irq;
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irq = i8259_irq();
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if (irq >= 0)
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do_IRQ(irq);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
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galileo_irq();
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else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
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via_pic_irq();
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else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
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do_IRQ(COBALT_CPU_IRQ + 3);
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else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
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do_IRQ(COBALT_CPU_IRQ + 4);
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else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
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do_IRQ(COBALT_CPU_IRQ + 5);
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else if (pending & CAUSEF_IP7) /* IRQ 23 */
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do_IRQ(COBALT_CPU_IRQ + 7);
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}
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static struct irqaction irq_via = {
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no_action, 0, { { 0, } }, "cascade", NULL, NULL
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};
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void __init arch_init_irq(void)
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{
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/*
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* Mask all Galileo interrupts. The Galileo
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* handler is set in cobalt_timer_setup()
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*/
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GT_WRITE(GT_INTRMASK_OFS, 0);
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init_i8259_irqs(); /* 0 ... 15 */
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mips_cpu_irq_init(); /* 16 ... 23 */
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/*
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* Mask all cpu interrupts
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* (except IE4, we already masked those at VIA level)
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*/
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change_c0_status(ST0_IM, IE_IRQ4);
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setup_irq(COBALT_VIA_IRQ, &irq_via);
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}
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