0f18597195
This patch adds support for the Gateworks Avila Network Platform in a separate set of setup files to the IXDP425. This is necessary now that a driver for the Avila CF card slot is available. It also adds support for a minor variant on the Avila board known as the Loft, which has a different number of maximum PCI devices. Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* include/asm-arm/arch-ixp4xx/irqs.h
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*
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* IRQ definitions for IXP4XX based systems
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*
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _ARCH_IXP4XX_IRQS_H_
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#define _ARCH_IXP4XX_IRQS_H_
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#define IRQ_IXP4XX_NPEA 0
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#define IRQ_IXP4XX_NPEB 1
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#define IRQ_IXP4XX_NPEC 2
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#define IRQ_IXP4XX_QM1 3
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#define IRQ_IXP4XX_QM2 4
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#define IRQ_IXP4XX_TIMER1 5
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#define IRQ_IXP4XX_GPIO0 6
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#define IRQ_IXP4XX_GPIO1 7
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#define IRQ_IXP4XX_PCI_INT 8
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#define IRQ_IXP4XX_PCI_DMA1 9
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#define IRQ_IXP4XX_PCI_DMA2 10
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#define IRQ_IXP4XX_TIMER2 11
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#define IRQ_IXP4XX_USB 12
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#define IRQ_IXP4XX_UART2 13
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#define IRQ_IXP4XX_TIMESTAMP 14
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#define IRQ_IXP4XX_UART1 15
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#define IRQ_IXP4XX_WDOG 16
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#define IRQ_IXP4XX_AHB_PMU 17
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#define IRQ_IXP4XX_XSCALE_PMU 18
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#define IRQ_IXP4XX_GPIO2 19
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#define IRQ_IXP4XX_GPIO3 20
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#define IRQ_IXP4XX_GPIO4 21
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#define IRQ_IXP4XX_GPIO5 22
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#define IRQ_IXP4XX_GPIO6 23
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#define IRQ_IXP4XX_GPIO7 24
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#define IRQ_IXP4XX_GPIO8 25
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#define IRQ_IXP4XX_GPIO9 26
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#define IRQ_IXP4XX_GPIO10 27
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#define IRQ_IXP4XX_GPIO11 28
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#define IRQ_IXP4XX_GPIO12 29
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#define IRQ_IXP4XX_SW_INT1 30
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#define IRQ_IXP4XX_SW_INT2 31
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#define IRQ_IXP4XX_USB_HOST 32
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#define IRQ_IXP4XX_I2C 33
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#define IRQ_IXP4XX_SSP 34
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#define IRQ_IXP4XX_TSYNC 35
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#define IRQ_IXP4XX_EAU_DONE 36
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#define IRQ_IXP4XX_SHA_DONE 37
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#define IRQ_IXP4XX_SWCP_PE 58
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#define IRQ_IXP4XX_QM_PE 60
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#define IRQ_IXP4XX_MCU_ECC 61
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#define IRQ_IXP4XX_EXP_PE 62
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/*
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* Only first 32 sources are valid if running on IXP42x systems
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*/
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#ifndef CONFIG_CPU_IXP46X
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#define NR_IRQS 32
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#else
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#define NR_IRQS 64
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#endif
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#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
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/*
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* IXDP425 board IRQs
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*/
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#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
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/*
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* Gateworks Avila board IRQs
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*/
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#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8
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/*
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* PrPMC1100 Board IRQs
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*/
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#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
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/*
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* ADI Coyote Board IRQs
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*/
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#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
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#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
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#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
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/*
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* NSLU2 board IRQs
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*/
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#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
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/*
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* NAS100D board IRQs
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*/
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#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
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#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
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#endif
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