2da2324793
The PCI controller IO base was not set in the au1000 pci code. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Alchemy/AMD Au1x00 pci support.
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*
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* Copyright 2001,2002,2003 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* Support for all devices (greater than 16) added by David Gathright.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/mach-au1x00/au1000.h>
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/* TBD */
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static struct resource pci_io_resource = {
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.start = (resource_size_t)PCI_IO_START,
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.end = (resource_size_t)PCI_IO_END,
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.name = "PCI IO space",
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.start = (resource_size_t)PCI_MEM_START,
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.end = (resource_size_t)PCI_MEM_END,
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.name = "PCI memory space",
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops au1x_pci_ops;
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static struct pci_controller au1x_controller = {
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.pci_ops = &au1x_pci_ops,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource,
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};
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
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static unsigned long virt_io_addr;
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#endif
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static int __init au1x_pci_setup(void)
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{
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
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virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
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Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
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if (!virt_io_addr) {
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printk(KERN_ERR "Unable to ioremap pci space\n");
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return 1;
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}
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au1x_controller.io_map_base = virt_io_addr;
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#ifdef CONFIG_DMA_NONCOHERENT
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{
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/*
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* Set the NC bit in controller for Au1500 pre-AC silicon
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*/
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u32 prid = read_c0_prid();
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if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
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au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
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Au1500_PCI_CFG);
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printk("Non-coherent PCI accesses enabled\n");
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}
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}
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#endif
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set_io_port_base(virt_io_addr);
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#endif
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register_pci_controller(&au1x_controller);
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return 0;
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}
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arch_initcall(au1x_pci_setup);
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