0d831770b1
This extends the current SH DMA API somewhat to support a proper virtual channel abstraction, and also works to represent this through the driver model by giving each DMAC its own platform device. There's also a few other minor changes to support a few new CPU subtypes, and make TEI generation for the SH DMAC configurable. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
172 lines
4.1 KiB
C
172 lines
4.1 KiB
C
/*
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* arch/sh/drivers/dma/dma-g2.c
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*
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* G2 bus DMA support
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*
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* Copyright (C) 2003, 2004 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <asm/mach/sysasic.h>
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#include <asm/mach/dma.h>
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#include <asm/dma.h>
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struct g2_channel {
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unsigned long g2_addr; /* G2 bus address */
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unsigned long root_addr; /* Root bus (SH-4) address */
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unsigned long size; /* Size (in bytes), 32-byte aligned */
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unsigned long direction; /* Transfer direction */
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unsigned long ctrl; /* Transfer control */
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unsigned long chan_enable; /* Channel enable */
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unsigned long xfer_enable; /* Transfer enable */
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unsigned long xfer_stat; /* Transfer status */
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} __attribute__ ((aligned(32)));
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struct g2_status {
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unsigned long g2_addr;
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unsigned long root_addr;
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unsigned long size;
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unsigned long status;
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} __attribute__ ((aligned(16)));
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struct g2_dma_info {
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struct g2_channel channel[G2_NR_DMA_CHANNELS];
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unsigned long pad1[G2_NR_DMA_CHANNELS];
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unsigned long wait_state;
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unsigned long pad2[10];
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unsigned long magic;
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struct g2_status status[G2_NR_DMA_CHANNELS];
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} __attribute__ ((aligned(256)));
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static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa05f7800;
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static irqreturn_t g2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* FIXME: Do some meaningful completion work here.. */
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return IRQ_HANDLED;
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}
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static struct irqaction g2_dma_irq = {
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.name = "g2 DMA handler",
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.handler = g2_dma_interrupt,
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.flags = SA_INTERRUPT,
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};
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static int g2_enable_dma(struct dma_channel *chan)
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{
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unsigned int chan_nr = chan->chan;
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g2_dma->channel[chan_nr].chan_enable = 1;
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g2_dma->channel[chan_nr].xfer_enable = 1;
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return 0;
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}
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static int g2_disable_dma(struct dma_channel *chan)
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{
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unsigned int chan_nr = chan->chan;
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g2_dma->channel[chan_nr].chan_enable = 0;
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g2_dma->channel[chan_nr].xfer_enable = 0;
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return 0;
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}
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static int g2_xfer_dma(struct dma_channel *chan)
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{
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unsigned int chan_nr = chan->chan;
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if (chan->sar & 31) {
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printk("g2dma: unaligned source 0x%lx\n", chan->sar);
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return -EINVAL;
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}
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if (chan->dar & 31) {
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printk("g2dma: unaligned dest 0x%lx\n", chan->dar);
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return -EINVAL;
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}
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/* Align the count */
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if (chan->count & 31)
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chan->count = (chan->count + (32 - 1)) & ~(32 - 1);
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/* Fixup destination */
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chan->dar += 0xa0800000;
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/* Fixup direction */
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chan->mode = !chan->mode;
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flush_icache_range((unsigned long)chan->sar, chan->count);
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g2_disable_dma(chan);
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g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0;
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g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0;
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g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000;
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g2_dma->channel[chan_nr].direction = chan->mode;
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/*
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* bit 0 - ???
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* bit 1 - if set, generate a hardware event on transfer completion
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* bit 2 - ??? something to do with suspend?
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*/
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g2_dma->channel[chan_nr].ctrl = 5; /* ?? */
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g2_enable_dma(chan);
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/* debug cruft */
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pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, "
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"0x%08lx, %ld, %ld, %ld, %ld\n",
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g2_dma->channel[chan_nr].size,
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g2_dma->channel[chan_nr].root_addr,
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g2_dma->channel[chan_nr].g2_addr,
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g2_dma->channel[chan_nr].direction,
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g2_dma->channel[chan_nr].ctrl,
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g2_dma->channel[chan_nr].chan_enable,
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g2_dma->channel[chan_nr].xfer_enable);
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return 0;
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}
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static struct dma_ops g2_dma_ops = {
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.xfer = g2_xfer_dma,
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};
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static struct dma_info g2_dma_info = {
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.name = "g2_dmac",
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.nr_channels = 4,
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.ops = &g2_dma_ops,
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.flags = DMAC_CHANNELS_TEI_CAPABLE,
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};
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static int __init g2_dma_init(void)
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{
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setup_irq(HW_EVENT_G2_DMA, &g2_dma_irq);
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/* Magic */
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g2_dma->wait_state = 27;
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g2_dma->magic = 0x4659404f;
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return register_dmac(&g2_dma_info);
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}
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static void __exit g2_dma_exit(void)
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{
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free_irq(HW_EVENT_G2_DMA, 0);
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unregister_dmac(&g2_dma_info);
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}
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subsys_initcall(g2_dma_init);
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module_exit(g2_dma_exit);
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MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
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MODULE_DESCRIPTION("G2 bus DMA driver");
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MODULE_LICENSE("GPL");
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