54e269ead6
Patch from Deepak Saxena The expansion bus on the IXP46x NPU can be configured for either 32MiB or 16MiB windows and changing the configuration causes the base address for each chip select for each region to change. Because of this, we cannot hardcode the physical base as we currently do. This patch checks the expansion bus configuration registers at runtime to determine the appropriate window size. Note that this requires that the bootloader already configured the device sizes appropriately, but I feel that is valid assumption to make as the bootloader must configure and access the flash window, the output display (LCD, LEDs, etc) window, and other expansion bus devices. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/*
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* include/asm-arm/arch-ixp4xx/nas100d.h
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*
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* NAS100D platform specific definitions
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*
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* Copyright (c) 2005 Tower Technologies
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*
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* Author: Alessandro Zummo <a.zummo@towertech.it>
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*
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* based on ixdp425.h:
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* Copyright 2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#error "Do not include this directly, instead #include <asm/hardware.h>"
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#endif
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#define NAS100D_SDA_PIN 6
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#define NAS100D_SCL_PIN 5
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/*
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* NAS100D PCI IRQs
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*/
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#define NAS100D_PCI_MAX_DEV 3
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#define NAS100D_PCI_IRQ_LINES 3
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/* PCI controller GPIO to IRQ pin mappings */
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#define NAS100D_PCI_INTA_PIN 11
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#define NAS100D_PCI_INTB_PIN 10
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#define NAS100D_PCI_INTC_PIN 9
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#define NAS100D_PCI_INTD_PIN 8
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#define NAS100D_PCI_INTE_PIN 7
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/* GPIO */
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#define NAS100D_GPIO0 0
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#define NAS100D_GPIO1 1
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#define NAS100D_GPIO2 2
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#define NAS100D_GPIO3 3
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#define NAS100D_GPIO4 4
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#define NAS100D_GPIO5 5
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#define NAS100D_GPIO6 6
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#define NAS100D_GPIO7 7
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#define NAS100D_GPIO8 8
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#define NAS100D_GPIO9 9
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#define NAS100D_GPIO10 10
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#define NAS100D_GPIO11 11
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#define NAS100D_GPIO12 12
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#define NAS100D_GPIO13 13
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#define NAS100D_GPIO14 14
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#define NAS100D_GPIO15 15
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/* Buttons */
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#define NAS100D_PB_GPIO NAS100D_GPIO14
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#define NAS100D_RB_GPIO NAS100D_GPIO4
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#define NAS100D_PO_GPIO NAS100D_GPIO12 /* power off */
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#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14
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#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4
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/*
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#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO)
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#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO)
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#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO)
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*/
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