23bdf86aa0
Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
182 lines
3.3 KiB
C
182 lines
3.3 KiB
C
/*
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* linux/include/asm-arm/proc-fns.h
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*
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* Copyright (C) 1997-1999 Russell King
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROCFNS_H
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#define __ASM_PROCFNS_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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/*
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* Work out if we need multiple CPU support
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*/
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#undef MULTI_CPU
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#undef CPU_NAME
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/*
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* CPU_NAME - the prefix for CPU related functions
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*/
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#ifdef CONFIG_CPU_32
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# ifdef CONFIG_CPU_ARM610
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm6
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM710
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm7
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM720T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm720
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM920T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm920
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM922T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm922
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM925T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm925
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM926T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm926
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# endif
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# endif
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# ifdef CONFIG_CPU_SA110
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_sa110
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# endif
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# endif
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# ifdef CONFIG_CPU_SA1100
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_sa1100
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM1020
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm1020
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM1020E
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm1020e
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM1022
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm1022
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM1026
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm1026
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# endif
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# endif
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# ifdef CONFIG_CPU_XSCALE
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_xscale
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# endif
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# endif
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# ifdef CONFIG_CPU_XSC3
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_xsc3
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# endif
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# endif
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# ifdef CONFIG_CPU_V6
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_v6
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# endif
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# endif
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#endif
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#ifndef __ASSEMBLY__
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#ifndef MULTI_CPU
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#include "asm/cpu-single.h"
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#else
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#include "asm/cpu-multi32.h"
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#endif
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#include <asm/memory.h>
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#define cpu_get_pgd() \
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({ \
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unsigned long pg; \
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__asm__("mrc p15, 0, %0, c2, c0, 0" \
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: "=r" (pg) : : "cc"); \
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pg &= ~0x3fff; \
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(pgd_t *)phys_to_virt(pg); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_PROCFNS_H */
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