38ce73ebd7
Add CP6 enable/disable sequences to the timekeeping code and the IRQ code. As a result, we can't depend on CP6 access being enabled when we enter get_irqnr_and_base anymore, so switch the latter over to using memory-mapped accesses for now. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
35 lines
957 B
ArmAsm
35 lines
957 B
ArmAsm
/*
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* include/asm-arm/arch-iop33x/entry-macro.S
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*
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* Low-level IRQ helper macros for IOP33x-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/arch/irqs.h>
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.macro disable_fiq
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.endm
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/*
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* Note: only deal with normal interrupts, not FIQ
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \irqnr, #0
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ldr \base, =IOP3XX_REG_ADDR(0x7A0)
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ldr \irqstat, [\base] @ Read IINTSRC0
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cmp \irqstat, #0
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bne 1002f
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ldr \irqstat, [\base, #4] @ Read IINTSRC1
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cmp \irqstat, #0
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beq 1001f
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clz \irqnr, \irqstat
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rsbs \irqnr,\irqnr,#31 @ recommend by RMK
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add \irqnr,\irqnr,#IRQ_IOP331_XINT8
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b 1001f
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1002: clz \irqnr, \irqstat
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rsbs \irqnr,\irqnr,#31 @ recommend by RMK
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add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
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1001:
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.endm
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