d0760b3bc8
The Atmel AT91SAM9263 processor includes many more integrated
peripherals than Atmel's previous ARM9-based AT91 processors, so this
has necessitated a few changes to the core AT91 support.
These changes are:
* The system peripheral I/O region we remap has increased from
0xFFFA0000..0xFFFFFFFF to 0xFFF78000..0xFFFFFFFF.
* The increased I/O region forces changes to entry-macro.S and
debug-macro.S due to ARM's limited immediate offset addressing
modes.
* Maximum number of GPIO banks increases to 5.
* 2 MMC controllers so the board-setup code needs to specify which
controller it wishes to use when calling at91_add_device_mmc().
Original patch from Nicolas Ferre.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
78 lines
4.2 KiB
C
78 lines
4.2 KiB
C
/*
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* include/asm-arm/arch-at91/at91sam9260_matrix.h
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*
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* Memory Controllers (MATRIX, EBI) - System peripherals registers.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9260_MATRIX_H
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#define AT91SAM9260_MATRIX_H
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#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
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#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
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#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
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#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
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#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
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#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
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#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
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#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
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#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
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#define AT91_MATRIX_ULBT_FOUR (2 << 0)
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#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
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#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
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#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
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#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
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#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
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#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
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#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
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#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
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#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
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#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
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#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
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#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
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#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
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#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
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#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
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#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
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#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
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#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
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#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
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#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
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#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
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#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
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#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
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#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
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#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
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#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
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#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
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#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
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#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
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#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
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#define AT91_MATRIX_CS1A_SMC (0 << 1)
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#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
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#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
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#define AT91_MATRIX_CS3A_SMC (0 << 3)
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#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
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#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
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#define AT91_MATRIX_CS4A_SMC (0 << 4)
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#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
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#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
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#define AT91_MATRIX_CS5A_SMC (0 << 5)
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#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
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#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
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#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
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#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
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#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
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#endif
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