13dff62d80
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/blackfin uses of the __cpuinit macros from
all C files. Currently blackfin does not have any __CPUINIT used in
assembly files.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Bob Liu <lliubbo@gmail.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: uclinux-dist-devel@blackfin.uclinux.org
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
/*
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* Blackfin cache control code (simpler control-style functions)
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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/* Invalidate the Entire Data cache by
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* clearing DMC[1:0] bits
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*/
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void blackfin_invalidate_entire_dcache(void)
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{
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u32 dmem = bfin_read_DMEM_CONTROL();
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bfin_write_DMEM_CONTROL(dmem & ~0xc);
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SSYNC();
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bfin_write_DMEM_CONTROL(dmem);
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SSYNC();
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}
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/* Invalidate the Entire Instruction cache by
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* clearing IMC bit
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*/
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void blackfin_invalidate_entire_icache(void)
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{
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u32 imem = bfin_read_IMEM_CONTROL();
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bfin_write_IMEM_CONTROL(imem & ~0x4);
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SSYNC();
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bfin_write_IMEM_CONTROL(imem);
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SSYNC();
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}
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#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
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static void
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bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
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unsigned long cplb_data, unsigned long mem_control,
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unsigned long mem_mask)
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{
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
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bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
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}
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_enable_cplb(mem_control, mem_mask);
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}
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#ifdef CONFIG_BFIN_ICACHE
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void bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
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(IMC | ENICPLB));
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}
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
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(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
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}
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#endif
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#endif
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