52650505fb
The OMAP1 clock code currently #includes a large .h file full of static
data structures. Instead, define the data in a .c file.
Russell King <linux@arm.linux.org.uk> proposed this new arrangement:
http://marc.info/?l=linux-omap&m=125967425908895&w=2
This patch also deals with most of the flagrant checkpatch violations.
While here, separate the mpu_rate data structures out into their own
files, opp.h and opp_data.c. In the long run, these mpu_rate tables
should be replaced with OPP code.
Also includes a patch from Felipe Balbi <felipe.balbi@nokia.com> to
mark omap1_clk_functions as __initdata to avoid a section warning:
http://patchwork.kernel.org/patch/64366/
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Felipe Balbi <felipe.balbi@nokia.com>
Cc: Nishanth Menon <nm@ti.com>
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
/*
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* linux/arch/arm/mach-omap1/io.c
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*
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* OMAP1 I/O mapping code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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#include <plat/mux.h>
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#include <plat/tc.h>
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#include "clock.h"
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extern void omap_check_revision(void);
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extern void omap_sram_init(void);
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extern void omapfb_reserve_sdram(void);
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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static struct map_desc omap_io_desc[] __initdata = {
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{
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.virtual = OMAP1_IO_VIRT,
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.pfn = __phys_to_pfn(OMAP1_IO_PHYS),
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.length = OMAP1_IO_SIZE,
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.type = MT_DEVICE
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}
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};
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#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
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static struct map_desc omap7xx_io_desc[] __initdata = {
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{
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.virtual = OMAP7XX_DSP_BASE,
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.pfn = __phys_to_pfn(OMAP7XX_DSP_START),
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.length = OMAP7XX_DSP_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = OMAP7XX_DSPREG_BASE,
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.pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
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.length = OMAP7XX_DSPREG_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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static struct map_desc omap1510_io_desc[] __initdata = {
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{
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.virtual = OMAP1510_DSP_BASE,
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.pfn = __phys_to_pfn(OMAP1510_DSP_START),
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.length = OMAP1510_DSP_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = OMAP1510_DSPREG_BASE,
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.pfn = __phys_to_pfn(OMAP1510_DSPREG_START),
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.length = OMAP1510_DSPREG_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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static struct map_desc omap16xx_io_desc[] __initdata = {
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{
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.virtual = OMAP16XX_DSP_BASE,
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.pfn = __phys_to_pfn(OMAP16XX_DSP_START),
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.length = OMAP16XX_DSP_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = OMAP16XX_DSPREG_BASE,
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.pfn = __phys_to_pfn(OMAP16XX_DSPREG_START),
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.length = OMAP16XX_DSPREG_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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/*
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* Maps common IO regions for omap1. This should only get called from
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* board specific init.
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*/
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void __init omap1_map_common_io(void)
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{
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iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
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/* Normally devicemaps_init() would flush caches and tlb after
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* mdesc->map_io(), but we must also do it here because of the CPU
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* revision check below.
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*/
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local_flush_tlb_all();
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flush_cache_all();
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/* We want to check CPU revision early for cpu_is_omapxxxx() macros.
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* IO space mapping must be initialized before we can do that.
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*/
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omap_check_revision();
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#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
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if (cpu_is_omap7xx()) {
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iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap15xx()) {
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iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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if (cpu_is_omap16xx()) {
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iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
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}
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#endif
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omap_sram_init();
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omapfb_reserve_sdram();
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}
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/*
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* Common low-level hardware init for omap1. This should only get called from
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* board specific init.
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*/
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void __init omap1_init_common_hw(void)
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{
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/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
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* on a Posted Write in the TIPB Bridge".
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*/
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omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
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omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
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/* Must init clocks early to assure that timer interrupt works
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*/
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omap1_clk_init();
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omap1_mux_init();
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}
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