48adbcf33b
This patch gets the DMA system for the S3C24XX ready for the S3C2443, which requires 6 dma channels at a different stride, and different base IRQ. The DMA system is now initialised from the same drivers which apply the DMA mappings, as well as removing the DMA sysdev intialisation out of the main init code (which is now being called from a sysdev probe, so cannot add a new sysdev) Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
181 lines
4.8 KiB
C
181 lines
4.8 KiB
C
/* linux/arch/arm/mach-s3c2410/dma.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 DMA selection
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*
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <asm/dma.h>
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#include <asm/arch/dma.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/dma.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-ac97.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/arch/regs-sdi.h>
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#include <asm/arch/regs-iis.h>
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#include <asm/arch/regs-spi.h>
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static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
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[DMACH_XD0] = {
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.name = "xdreq0",
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.channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
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},
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[DMACH_XD1] = {
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.name = "xdreq1",
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.channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
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},
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[DMACH_SDI] = {
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.name = "sdi",
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.channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
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.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
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.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
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.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_SPI0] = {
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.name = "spi0",
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.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
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},
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[DMACH_SPI1] = {
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.name = "spi1",
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.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
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},
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[DMACH_UART0] = {
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.name = "uart0",
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.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
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},
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[DMACH_UART1] = {
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.name = "uart1",
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.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
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},
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[DMACH_UART2] = {
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.name = "uart2",
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.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
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},
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[DMACH_TIMER] = {
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.name = "timer",
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.channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
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.channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
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.channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
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},
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[DMACH_I2S_IN] = {
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.name = "i2s-sdi",
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.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
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.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
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.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_I2S_OUT] = {
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.name = "i2s-sdo",
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.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
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.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_USB_EP1] = {
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.name = "usb-ep1",
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.channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
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},
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[DMACH_USB_EP2] = {
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.name = "usb-ep2",
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.channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
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},
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[DMACH_USB_EP3] = {
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.name = "usb-ep3",
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.channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
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},
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[DMACH_USB_EP4] = {
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.name = "usb-ep4",
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.channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
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},
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};
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static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map)
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{
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chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
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}
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static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
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.select = s3c2410_dma_select,
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.dcon_mask = 7 << 24,
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.map = s3c2410_dma_mappings,
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.map_size = ARRAY_SIZE(s3c2410_dma_mappings),
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};
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static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
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.channels = {
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[DMACH_SDI] = {
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.list = {
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[0] = 3 | DMA_CH_VALID,
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[1] = 2 | DMA_CH_VALID,
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[2] = 0 | DMA_CH_VALID,
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},
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},
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[DMACH_I2S_IN] = {
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.list = {
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[0] = 1 | DMA_CH_VALID,
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[1] = 2 | DMA_CH_VALID,
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},
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},
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},
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};
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static int s3c2410_dma_add(struct sys_device *sysdev)
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{
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s3c2410_dma_init();
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s3c24xx_dma_order_set(&s3c2410_dma_order);
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return s3c24xx_dma_init_map(&s3c2410_dma_sel);
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}
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#if defined(CONFIG_CPU_S3C2410)
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static struct sysdev_driver s3c2410_dma_driver = {
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.add = s3c2410_dma_add,
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};
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static int __init s3c2410_dma_drvinit(void)
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{
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return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
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}
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arch_initcall(s3c2410_dma_drvinit);
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#endif
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#if defined(CONFIG_CPU_S3C2442)
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/* S3C2442 DMA contains the same selection table as the S3C2410 */
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static struct sysdev_driver s3c2442_dma_driver = {
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.add = s3c2410_dma_add,
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};
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static int __init s3c2442_dma_drvinit(void)
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{
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return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
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}
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arch_initcall(s3c2442_dma_drvinit);
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#endif
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