414 lines
11 KiB
C
414 lines
11 KiB
C
/*
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* EHCI HCD (Host Controller Driver) PCI Bus Glue.
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*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef CONFIG_PCI
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#error "This file is PCI bus glue. CONFIG_PCI must be defined."
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#endif
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/*-------------------------------------------------------------------------*/
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/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
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* off the controller (maybe it can boot from highspeed USB disks).
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*/
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static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
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{
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struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
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/* always say Linux will own the hardware */
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pci_write_config_byte(pdev, where + 3, 1);
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/* maybe wait a while for BIOS to respond */
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if (cap & (1 << 16)) {
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int msec = 5000;
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do {
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msleep(10);
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msec -= 10;
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pci_read_config_dword(pdev, where, &cap);
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} while ((cap & (1 << 16)) && msec);
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if (cap & (1 << 16)) {
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ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
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where, cap);
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// some BIOS versions seem buggy...
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// return 1;
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ehci_warn (ehci, "continuing after BIOS bug...\n");
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/* disable all SMIs, and clear "BIOS owns" flag */
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pci_write_config_dword(pdev, where + 4, 0);
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pci_write_config_byte(pdev, where + 2, 0);
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} else
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ehci_dbg(ehci, "BIOS handoff succeeded\n");
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}
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return 0;
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}
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/* called by khubd or root hub init threads */
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static int ehci_pci_reset (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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u32 temp;
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unsigned count = 256/4;
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spin_lock_init (&ehci->lock);
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
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dbg_hcs_params (ehci, "reset");
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dbg_hcc_params (ehci, "reset");
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = readl (&ehci->caps->hcs_params);
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
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ehci->is_tdi_rh_tt = 1;
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tdi_reset (ehci);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info (ehci, "ignoring AMD8111 (errata)\n");
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return -EIO;
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_31BIT_MASK) < 0)
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ehci_warn (ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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}
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break;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability (pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = readl (&ehci->debug->control);
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ehci_info (ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
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} else
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temp = 0;
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/* EHCI 0.96 and later may have "extended capabilities" */
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while (temp && count--) {
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u32 cap;
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pci_read_config_dword (to_pci_dev(hcd->self.controller),
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temp, &cap);
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ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff */
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if (bios_handoff (ehci, temp, cap) != 0)
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return -EOPNOTSUPP;
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break;
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case 0: /* illegal reserved capability */
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ehci_warn (ehci, "illegal capability!\n");
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cap = 0;
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/* FALLTHROUGH */
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default: /* unknown */
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break;
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}
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temp = (cap >> 8) & 0xff;
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}
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if (!count) {
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ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
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return -EIO;
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}
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if (ehci_is_TDI(ehci))
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ehci_reset (ehci);
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ehci_port_power (ehci, 0);
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
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ehci_dbg (ehci, "bogus port configuration: "
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"cc=%d x pcc=%d < ports=%d\n",
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HCS_N_CC(ehci->hcs_params),
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HCS_N_PCC(ehci->hcs_params),
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HCS_N_PORTS(ehci->hcs_params));
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev;
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pdev = to_pci_dev(hcd->self.controller);
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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}
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}
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/* force HC to halt state */
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return ehci_halt (ehci);
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}
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static int ehci_pci_start (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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int result = 0;
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev;
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u16 port_wake;
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pdev = to_pci_dev(hcd->self.controller);
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* port wake capability, reported by boot firmware */
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pci_read_config_word(pdev, 0x62, &port_wake);
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hcd->can_wakeup = (port_wake & 1) != 0;
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/* help hc dma work well with cachelines */
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result = pci_set_mwi(pdev);
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if (result)
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ehci_dbg(ehci, "unable to enable MWI - not fatal.\n");
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}
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return ehci_run (hcd);
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}
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/* always called by thread; normally rmmod */
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static void ehci_pci_stop (struct usb_hcd *hcd)
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{
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ehci_stop (hcd);
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}
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_PM
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/* suspend/resume, section 4.3 */
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/* These routines rely on the bus (pci, platform, etc)
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* to handle powerdown and wakeup, and currently also on
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* transceivers that don't need any software attention to set up
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* the right sort of wakeup.
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*/
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static int ehci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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if (time_before (jiffies, ehci->next_statechange))
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msleep (100);
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#ifdef CONFIG_USB_SUSPEND
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(void) usb_suspend_device (hcd->self.root_hub);
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#else
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usb_lock_device (hcd->self.root_hub);
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(void) ehci_bus_suspend (hcd);
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usb_unlock_device (hcd->self.root_hub);
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#endif
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// save (PCI) FLADJ in case of Vaux power loss
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// ... we'd only use it to handle clock skew
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return 0;
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}
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static int ehci_pci_resume (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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unsigned port;
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struct usb_device *root = hcd->self.root_hub;
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int retval = -EINVAL;
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// maybe restore (PCI) FLADJ
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if (time_before (jiffies, ehci->next_statechange))
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msleep (100);
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/* If any port is suspended (or owned by the companion),
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* we know we can/must resume the HC (and mustn't reset it).
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*/
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for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
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u32 status;
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port--;
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status = readl (&ehci->regs->port_status [port]);
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if (!(status & PORT_POWER))
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continue;
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if (status & (PORT_SUSPEND | PORT_OWNER)) {
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down (&hcd->self.root_hub->serialize);
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retval = ehci_bus_resume (hcd);
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up (&hcd->self.root_hub->serialize);
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break;
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}
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if (!root->children [port])
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continue;
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dbg_port (ehci, __FUNCTION__, port + 1, status);
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usb_set_device_state (root->children[port],
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USB_STATE_NOTATTACHED);
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}
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/* Else reset, to cope with power loss or flush-to-storage
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* style "resume" having activated BIOS during reboot.
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*/
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if (port == 0) {
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(void) ehci_halt (ehci);
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(void) ehci_reset (ehci);
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(void) ehci_pci_reset (hcd);
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/* emptying the schedule aborts any urbs */
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spin_lock_irq (&ehci->lock);
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if (ehci->reclaim)
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ehci->reclaim_ready = 1;
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ehci_work (ehci, NULL);
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spin_unlock_irq (&ehci->lock);
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/* restart; khubd will disconnect devices */
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retval = ehci_run (hcd);
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/* here we "know" root ports should always stay powered;
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* but some controllers may lose all power.
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*/
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ehci_port_power (ehci, 1);
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}
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return retval;
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}
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#endif
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static const struct hc_driver ehci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2,
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/*
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* basic lifecycle operations
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*/
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.reset = ehci_pci_reset,
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.start = ehci_pci_start,
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#ifdef CONFIG_PM
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.suspend = ehci_pci_suspend,
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.resume = ehci_pci_resume,
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#endif
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.stop = ehci_pci_stop,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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/*
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* scheduling support
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*/
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.get_frame_number = ehci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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};
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids [] = { {
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/* handle any USB 2.0 EHCI controller */
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PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
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.driver_data = (unsigned long) &ehci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE (pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ehci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = usb_hcd_pci_probe,
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.remove = usb_hcd_pci_remove,
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#ifdef CONFIG_PM
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.suspend = usb_hcd_pci_suspend,
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.resume = usb_hcd_pci_resume,
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#endif
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};
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static int __init ehci_hcd_pci_init (void)
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{
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if (usb_disabled())
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return -ENODEV;
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pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
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hcd_name,
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sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
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sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
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return pci_register_driver (&ehci_pci_driver);
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}
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module_init (ehci_hcd_pci_init);
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static void __exit ehci_hcd_pci_cleanup (void)
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{
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pci_unregister_driver (&ehci_pci_driver);
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}
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module_exit (ehci_hcd_pci_cleanup);
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