3b520b238e
There has been some discuss about solving the SMP MTRR suspend/resume breakage, but I didn't find a patch for it. This is an intent for it. The basic idea is moving mtrr initializing into cpu_identify for all APs (so it works for cpu hotplug). For BP, restore_processor_state is responsible for restoring MTRR. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Acked-by: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
158 lines
4.4 KiB
C
158 lines
4.4 KiB
C
/*
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* Suspend support specific for i386.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/poll.h>
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#include <linux/delay.h>
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#include <linux/sysrq.h>
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#include <linux/proc_fs.h>
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#include <linux/irq.h>
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#include <linux/pm.h>
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#include <linux/device.h>
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#include <linux/suspend.h>
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#include <asm/uaccess.h>
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#include <asm/acpi.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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#include <asm/proto.h>
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struct saved_context saved_context;
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unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
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unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
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unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
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unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
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unsigned long saved_context_eflags;
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void __save_processor_state(struct saved_context *ctxt)
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{
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
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asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
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asm volatile ("str %0" : "=m" (ctxt->tr));
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
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/* EFER should be constant for kernel version, no need to handle it. */
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/*
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* segment registers
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*/
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asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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rdmsrl(MSR_FS_BASE, ctxt->fs_base);
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rdmsrl(MSR_GS_BASE, ctxt->gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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/*
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* control registers
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*/
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asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
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asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
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asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
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asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
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asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
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}
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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static void
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do_fpu_end(void)
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{
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/* restore FPU regs if necessary */
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/* Do it out of line so that gcc does not move cr0 load to some stupid place */
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kernel_fpu_end();
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mxcsr_feature_mask_init();
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}
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void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
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asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
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asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
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asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
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asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
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asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
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/*
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* segment registers
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*/
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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}
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
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cpu_gdt_table[cpu][GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7){
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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}
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}
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