9ffa739606
This patch adds support for the other three palette formats possible with
the PXA LCD controller. This is required on boards where an LCD is connected
with all its 18 bits. With this patch, it's possible to use an 8-bit mode
with 18-bit palette entries. This used to be possible in 2.4 kernels but
disappeared in 2.6. With current kernels, you can only get wrong colours
out of an LCD connected this way.
Users can choose the palette format by doing something like this
in their board definition:
static struct pxafb_mach_info my_fb_info = {
[...]
.lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_PDFOR_3,
.lccr4 = LCCR4_PAL_FOR_2,
[...]
};
Signed-off-by: Hans J. Koch <hjk@linutronix.de>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/pxafb.h
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*
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* Support for the xscale frame buffer.
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*
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* Author: Jean-Frederic Clere
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* Created: Sep 22, 2003
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* Copyright: jfclere@sinix.net
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/fb.h>
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/*
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* This structure describes the machine which we are running on.
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* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
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* of linux/drivers/video/pxafb.c
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*/
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struct pxafb_mode_info {
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u_long pixclock;
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u_short xres;
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u_short yres;
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u_char bpp;
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u_char hsync_len;
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u_char left_margin;
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u_char right_margin;
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u_char vsync_len;
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u_char upper_margin;
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u_char lower_margin;
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u_char sync;
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u_int cmap_greyscale:1,
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unused:31;
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};
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struct pxafb_mach_info {
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struct pxafb_mode_info *modes;
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unsigned int num_modes;
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u_int fixed_modes:1,
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cmap_inverse:1,
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cmap_static:1,
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unused:29;
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/* The following should be defined in LCCR0
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* LCCR0_Act or LCCR0_Pas Active or Passive
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* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
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* LCCR0_Mono or LCCR0_Color Mono/Color
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* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
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* LCCR0_DMADel(Tcpu) (optional) DMA request delay
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*
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* The following should not be defined in LCCR0:
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* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
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* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
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*/
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u_int lccr0;
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/* The following should be defined in LCCR3
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* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
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* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
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* LCCR3_Acb(X) AB Bias pin frequency
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* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
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*
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* The following should not be defined in LCCR3
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* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
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*/
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u_int lccr3;
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/* The following should be defined in LCCR4
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* LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
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*
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* All other bits in LCCR4 should be left alone.
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*/
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u_int lccr4;
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void (*pxafb_backlight_power)(int);
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void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
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};
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void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
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void set_pxa_fb_parent(struct device *parent_dev);
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unsigned long pxafb_get_hsync_time(struct device *dev);
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