078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
171 lines
4.6 KiB
ArmAsm
171 lines
4.6 KiB
ArmAsm
/*
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* Copyright (C) 2001,2002,2003 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/cacheops.h>
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#include <asm/sibyte/board.h>
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#define C0_ERRCTL $26 /* CP0: Error info */
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#define C0_CERR_I $27 /* CP0: Icache error */
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#define C0_CERR_D $27,1 /* CP0: Dcache error */
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/*
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* Based on SiByte sample software cache-err/cerr.S
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* CVS revision 1.8. Only the 'unrecoverable' case
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* is changed.
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*/
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.set mips64
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.set noreorder
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.set noat
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/*
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* sb1_cerr_vec: code to be copied to the Cache Error
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* Exception vector. The code must be pushed out to memory
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* (either by copying to Kseg0 and Kseg1 both, or by flushing
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* the L1 and L2) since it is fetched as 0xa0000100.
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*
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* NOTE: Be sure this handler is at most 28 instructions long
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* since the final 16 bytes of the exception vector memory
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* (0x170-0x17f) are used to preserve k0, k1, and ra.
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*/
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LEAF(except_vec2_sb1)
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/*
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* If this error is recoverable, we need to exit the handler
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* without having dirtied any registers. To do this,
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* save/restore k0 and k1 from low memory (Useg is direct
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* mapped while ERL=1). Note that we can't save to a
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* CPU-specific location without ruining a register in the
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* process. This means we are vulnerable to data corruption
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* whenever the handler is reentered by a second CPU.
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*/
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sd k0,0x170($0)
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sd k1,0x178($0)
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#ifdef CONFIG_SB1_CEX_ALWAYS_FATAL
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j handle_vec2_sb1
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nop
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#else
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/*
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* M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
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* if we can fast-path out of here for a h/w-recovered error.
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*/
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mfc0 k1,C0_ERRCTL
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bgtz k1,attempt_recovery
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sll k0,k1,1
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recovered_dcache:
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/*
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* Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
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* Ought to log the occurrence of this recovered dcache error.
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*/
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b recovered
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mtc0 $0,C0_CERR_D
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attempt_recovery:
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/*
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* k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31. Any
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* Dcache errors we can recover from will take more extensive
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* processing. For now, they are considered "unrecoverable".
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* Note that 'DC' becoming set (outside of ERL mode) will
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* cause 'IC' to clear; so if there's an Icache error, we'll
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* only find out about it if we recover from this error and
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* continue executing.
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*/
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bltz k0,unrecoverable
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sll k0,1
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/*
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* k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31. If an
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* Icache error isn't indicated, I'm not sure why we got here.
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* Consider that case "unrecoverable" for now.
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*/
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bgez k0,unrecoverable
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attempt_icache_recovery:
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/*
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* External icache errors are due to uncorrectable ECC errors
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* in the L2 cache or Memory Controller and cannot be
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* recovered here.
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*/
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mfc0 k0,C0_CERR_I /* delay slot */
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li k1,1 << 26 /* ICACHE_EXTERNAL */
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and k1,k0
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bnez k1,unrecoverable
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andi k0,0x1fe0
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/*
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* Since the error is internal, the 'IDX' field from
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* CacheErr-I is valid and we can just invalidate all blocks
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* in that set.
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*/
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cache Index_Invalidate_I,(0<<13)(k0)
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cache Index_Invalidate_I,(1<<13)(k0)
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cache Index_Invalidate_I,(2<<13)(k0)
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cache Index_Invalidate_I,(3<<13)(k0)
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/* Ought to log this recovered icache error */
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recovered:
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/* Restore the saved registers */
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ld k0,0x170($0)
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ld k1,0x178($0)
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eret
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unrecoverable:
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/* Unrecoverable Icache or Dcache error; log it and/or fail */
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j handle_vec2_sb1
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nop
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#endif
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END(except_vec2_sb1)
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LEAF(handle_vec2_sb1)
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mfc0 k0,CP0_CONFIG
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li k1,~CONF_CM_CMASK
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and k0,k0,k1
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ori k0,k0,CONF_CM_UNCACHED
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mtc0 k0,CP0_CONFIG
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SSNOP
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SSNOP
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SSNOP
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SSNOP
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bnezl $0, 1f
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1:
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mfc0 k0, CP0_STATUS
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sll k0, k0, 3 # check CU0 (kernel?)
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bltz k0, 2f
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nop
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/* Get a valid Kseg0 stack pointer. Any task's stack pointer
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* will do, although if we ever want to resume execution we
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* better not have corrupted any state. */
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get_saved_sp
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move sp, k1
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2:
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j sb1_cache_error
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nop
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END(handle_vec2_sb1)
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