d1d25aaba8
This patch fixes several whitespace issues. Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
292 lines
6.9 KiB
C
292 lines
6.9 KiB
C
/*
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* linux/drivers/net/ehea/ehea_hw.h
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*
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* eHEA ethernet device driver for IBM eServer System p
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*
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* (C) Copyright IBM Corp. 2006
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*
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* Authors:
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* Christoph Raisch <raisch@de.ibm.com>
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* Jan-Bernd Themann <themann@de.ibm.com>
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* Thomas Klein <tklein@de.ibm.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __EHEA_HW_H__
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#define __EHEA_HW_H__
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#define QPX_SQA_VALUE EHEA_BMASK_IBM(48,63)
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#define QPX_RQ1A_VALUE EHEA_BMASK_IBM(48,63)
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#define QPX_RQ2A_VALUE EHEA_BMASK_IBM(48,63)
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#define QPX_RQ3A_VALUE EHEA_BMASK_IBM(48,63)
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#define QPTEMM_OFFSET(x) offsetof(struct ehea_qptemm, x)
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struct ehea_qptemm {
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u64 qpx_hcr;
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u64 qpx_c;
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u64 qpx_herr;
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u64 qpx_aer;
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u64 qpx_sqa;
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u64 qpx_sqc;
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u64 qpx_rq1a;
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u64 qpx_rq1c;
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u64 qpx_st;
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u64 qpx_aerr;
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u64 qpx_tenure;
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u64 qpx_reserved1[(0x098 - 0x058) / 8];
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u64 qpx_portp;
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u64 qpx_reserved2[(0x100 - 0x0A0) / 8];
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u64 qpx_t;
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u64 qpx_sqhp;
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u64 qpx_sqptp;
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u64 qpx_reserved3[(0x140 - 0x118) / 8];
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u64 qpx_sqwsize;
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u64 qpx_reserved4[(0x170 - 0x148) / 8];
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u64 qpx_sqsize;
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u64 qpx_reserved5[(0x1B0 - 0x178) / 8];
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u64 qpx_sigt;
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u64 qpx_wqecnt;
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u64 qpx_rq1hp;
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u64 qpx_rq1ptp;
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u64 qpx_rq1size;
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u64 qpx_reserved6[(0x220 - 0x1D8) / 8];
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u64 qpx_rq1wsize;
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u64 qpx_reserved7[(0x240 - 0x228) / 8];
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u64 qpx_pd;
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u64 qpx_scqn;
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u64 qpx_rcqn;
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u64 qpx_aeqn;
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u64 reserved49;
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u64 qpx_ram;
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u64 qpx_reserved8[(0x300 - 0x270) / 8];
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u64 qpx_rq2a;
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u64 qpx_rq2c;
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u64 qpx_rq2hp;
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u64 qpx_rq2ptp;
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u64 qpx_rq2size;
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u64 qpx_rq2wsize;
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u64 qpx_rq2th;
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u64 qpx_rq3a;
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u64 qpx_rq3c;
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u64 qpx_rq3hp;
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u64 qpx_rq3ptp;
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u64 qpx_rq3size;
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u64 qpx_rq3wsize;
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u64 qpx_rq3th;
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u64 qpx_lpn;
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u64 qpx_reserved9[(0x400 - 0x378) / 8];
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u64 reserved_ext[(0x500 - 0x400) / 8];
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u64 reserved2[(0x1000 - 0x500) / 8];
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};
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#define MRx_HCR_LPARID_VALID EHEA_BMASK_IBM(0, 0)
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#define MRMWMM_OFFSET(x) offsetof(struct ehea_mrmwmm, x)
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struct ehea_mrmwmm {
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u64 mrx_hcr;
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u64 mrx_c;
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u64 mrx_herr;
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u64 mrx_aer;
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u64 mrx_pp;
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u64 reserved1;
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u64 reserved2;
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u64 reserved3;
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u64 reserved4[(0x200 - 0x40) / 8];
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u64 mrx_ctl[64];
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};
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#define QPEDMM_OFFSET(x) offsetof(struct ehea_qpedmm, x)
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struct ehea_qpedmm {
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u64 reserved0[(0x400) / 8];
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u64 qpedx_phh;
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u64 qpedx_ppsgp;
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u64 qpedx_ppsgu;
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u64 qpedx_ppdgp;
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u64 qpedx_ppdgu;
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u64 qpedx_aph;
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u64 qpedx_apsgp;
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u64 qpedx_apsgu;
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u64 qpedx_apdgp;
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u64 qpedx_apdgu;
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u64 qpedx_apav;
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u64 qpedx_apsav;
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u64 qpedx_hcr;
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u64 reserved1[4];
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u64 qpedx_rrl0;
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u64 qpedx_rrrkey0;
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u64 qpedx_rrva0;
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u64 reserved2;
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u64 qpedx_rrl1;
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u64 qpedx_rrrkey1;
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u64 qpedx_rrva1;
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u64 reserved3;
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u64 qpedx_rrl2;
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u64 qpedx_rrrkey2;
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u64 qpedx_rrva2;
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u64 reserved4;
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u64 qpedx_rrl3;
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u64 qpedx_rrrkey3;
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u64 qpedx_rrva3;
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};
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#define CQX_FECADDER EHEA_BMASK_IBM(32, 63)
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#define CQX_FEC_CQE_CNT EHEA_BMASK_IBM(32, 63)
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#define CQX_N1_GENERATE_COMP_EVENT EHEA_BMASK_IBM(0, 0)
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#define CQX_EP_EVENT_PENDING EHEA_BMASK_IBM(0, 0)
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#define CQTEMM_OFFSET(x) offsetof(struct ehea_cqtemm, x)
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struct ehea_cqtemm {
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u64 cqx_hcr;
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u64 cqx_c;
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u64 cqx_herr;
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u64 cqx_aer;
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u64 cqx_ptp;
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u64 cqx_tp;
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u64 cqx_fec;
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u64 cqx_feca;
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u64 cqx_ep;
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u64 cqx_eq;
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u64 reserved1;
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u64 cqx_n0;
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u64 cqx_n1;
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u64 reserved2[(0x1000 - 0x60) / 8];
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};
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#define EQTEMM_OFFSET(x) offsetof(struct ehea_eqtemm, x)
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struct ehea_eqtemm {
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u64 eqx_hcr;
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u64 eqx_c;
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u64 eqx_herr;
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u64 eqx_aer;
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u64 eqx_ptp;
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u64 eqx_tp;
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u64 eqx_ssba;
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u64 eqx_psba;
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u64 eqx_cec;
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u64 eqx_meql;
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u64 eqx_xisbi;
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u64 eqx_xisc;
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u64 eqx_it;
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};
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/*
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* These access functions will be changed when the dissuccsion about
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* the new access methods for POWER has settled.
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*/
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static inline u64 epa_load(struct h_epa epa, u32 offset)
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{
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return __raw_readq((void __iomem *)(epa.addr + offset));
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}
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static inline void epa_store(struct h_epa epa, u32 offset, u64 value)
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{
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__raw_writeq(value, (void __iomem *)(epa.addr + offset));
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epa_load(epa, offset); /* synchronize explicitly to eHEA */
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}
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static inline void epa_store_acc(struct h_epa epa, u32 offset, u64 value)
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{
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__raw_writeq(value, (void __iomem *)(epa.addr + offset));
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}
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#define epa_store_eq(epa, offset, value)\
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epa_store(epa, EQTEMM_OFFSET(offset), value)
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#define epa_load_eq(epa, offset)\
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epa_load(epa, EQTEMM_OFFSET(offset))
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#define epa_store_cq(epa, offset, value)\
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epa_store(epa, CQTEMM_OFFSET(offset), value)
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#define epa_load_cq(epa, offset)\
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epa_load(epa, CQTEMM_OFFSET(offset))
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#define epa_store_qp(epa, offset, value)\
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epa_store(epa, QPTEMM_OFFSET(offset), value)
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#define epa_load_qp(epa, offset)\
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epa_load(epa, QPTEMM_OFFSET(offset))
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#define epa_store_qped(epa, offset, value)\
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epa_store(epa, QPEDMM_OFFSET(offset), value)
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#define epa_load_qped(epa, offset)\
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epa_load(epa, QPEDMM_OFFSET(offset))
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#define epa_store_mrmw(epa, offset, value)\
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epa_store(epa, MRMWMM_OFFSET(offset), value)
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#define epa_load_mrmw(epa, offset)\
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epa_load(epa, MRMWMM_OFFSET(offset))
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#define epa_store_base(epa, offset, value)\
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epa_store(epa, HCAGR_OFFSET(offset), value)
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#define epa_load_base(epa, offset)\
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epa_load(epa, HCAGR_OFFSET(offset))
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static inline void ehea_update_sqa(struct ehea_qp *qp, u16 nr_wqes)
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{
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struct h_epa epa = qp->epas.kernel;
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epa_store_acc(epa, QPTEMM_OFFSET(qpx_sqa),
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EHEA_BMASK_SET(QPX_SQA_VALUE, nr_wqes));
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}
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static inline void ehea_update_rq3a(struct ehea_qp *qp, u16 nr_wqes)
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{
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struct h_epa epa = qp->epas.kernel;
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epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq3a),
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EHEA_BMASK_SET(QPX_RQ1A_VALUE, nr_wqes));
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}
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static inline void ehea_update_rq2a(struct ehea_qp *qp, u16 nr_wqes)
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{
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struct h_epa epa = qp->epas.kernel;
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epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq2a),
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EHEA_BMASK_SET(QPX_RQ2A_VALUE, nr_wqes));
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}
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static inline void ehea_update_rq1a(struct ehea_qp *qp, u16 nr_wqes)
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{
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struct h_epa epa = qp->epas.kernel;
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epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq1a),
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EHEA_BMASK_SET(QPX_RQ3A_VALUE, nr_wqes));
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}
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static inline void ehea_update_feca(struct ehea_cq *cq, u32 nr_cqes)
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{
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struct h_epa epa = cq->epas.kernel;
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epa_store_acc(epa, CQTEMM_OFFSET(cqx_feca),
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EHEA_BMASK_SET(CQX_FECADDER, nr_cqes));
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}
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static inline void ehea_reset_cq_n1(struct ehea_cq *cq)
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{
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struct h_epa epa = cq->epas.kernel;
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epa_store_cq(epa, cqx_n1,
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EHEA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, 1));
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}
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static inline void ehea_reset_cq_ep(struct ehea_cq *my_cq)
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{
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struct h_epa epa = my_cq->epas.kernel;
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epa_store_acc(epa, CQTEMM_OFFSET(cqx_ep),
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EHEA_BMASK_SET(CQX_EP_EVENT_PENDING, 0));
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}
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#endif /* __EHEA_HW_H__ */
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