5209487963
* Fixed up top level compatible property for all boards * Removed explicit linux,phandle usage. Use references and labels now * Fixed phy-phandles for TSEC3/4 in mpc8548cds.dts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
288 lines
6.3 KiB
Text
288 lines
6.3 KiB
Text
/*
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* MPC8560 ADS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8560ADS";
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compatible = "MPC8560ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <04ead9a0>;
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bus-frequency = <13ab6680>;
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clock-frequency = <312c8040>;
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32-bit;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 10000000>;
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};
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soc8560@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <13ab6680>;
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mdio@24520 {
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <35 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <35 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <37 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <37 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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address = [ 00 00 0C 00 00 FD ];
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interrupts = <d 2 e 2 12 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <25000 1000>;
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address = [ 00 00 0C 00 01 FD ];
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interrupts = <13 2 14 2 18 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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pci@8000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "85xx";
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device_type = "pci";
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reg = <8000 400>;
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clock-frequency = <3f940aa>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x2 */
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1000 0 0 1 &mpic 31 1
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1000 0 0 2 &mpic 32 1
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1000 0 0 3 &mpic 33 1
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1000 0 0 4 &mpic 34 1
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/* IDSEL 0x3 */
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1800 0 0 1 &mpic 34 1
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1800 0 0 2 &mpic 31 1
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1800 0 0 3 &mpic 32 1
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1800 0 0 4 &mpic 33 1
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/* IDSEL 0x4 */
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2000 0 0 1 &mpic 33 1
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2000 0 0 2 &mpic 34 1
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2000 0 0 3 &mpic 31 1
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2000 0 0 4 &mpic 32 1
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/* IDSEL 0x5 */
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2800 0 0 1 &mpic 32 1
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2800 0 0 2 &mpic 33 1
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2800 0 0 3 &mpic 34 1
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2800 0 0 4 &mpic 31 1
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/* IDSEL 12 */
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6000 0 0 1 &mpic 31 1
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6000 0 0 2 &mpic 32 1
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6000 0 0 3 &mpic 33 1
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6000 0 0 4 &mpic 34 1
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/* IDSEL 13 */
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6800 0 0 1 &mpic 34 1
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6800 0 0 2 &mpic 31 1
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6800 0 0 3 &mpic 32 1
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6800 0 0 4 &mpic 33 1
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/* IDSEL 14*/
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7000 0 0 1 &mpic 33 1
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7000 0 0 2 &mpic 34 1
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7000 0 0 3 &mpic 31 1
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7000 0 0 4 &mpic 32 1
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/* IDSEL 15 */
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7800 0 0 1 &mpic 32 1
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7800 0 0 2 &mpic 33 1
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7800 0 0 3 &mpic 34 1
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7800 0 0 4 &mpic 31 1
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/* IDSEL 18 */
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9000 0 0 1 &mpic 31 1
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9000 0 0 2 &mpic 32 1
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9000 0 0 3 &mpic 33 1
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9000 0 0 4 &mpic 34 1
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/* IDSEL 19 */
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9800 0 0 1 &mpic 34 1
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9800 0 0 2 &mpic 31 1
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9800 0 0 3 &mpic 32 1
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9800 0 0 4 &mpic 33 1
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/* IDSEL 20 */
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a000 0 0 1 &mpic 33 1
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a000 0 0 2 &mpic 34 1
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a000 0 0 3 &mpic 31 1
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a000 0 0 4 &mpic 32 1
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/* IDSEL 21 */
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a800 0 0 1 &mpic 32 1
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a800 0 0 2 &mpic 33 1
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a800 0 0 3 &mpic 34 1
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a800 0 0 4 &mpic 31 1>;
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interrupt-parent = <&mpic>;
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interrupts = <8 0>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 01000000>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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built-in;
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device_type = "open-pic";
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};
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cpm@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "cpm";
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model = "CPM2";
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ranges = <0 0 c0000>;
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reg = <80000 40000>;
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command-proc = <919c0>;
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brg-frequency = <9d5b340>;
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1e 0>;
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interrupt-parent = <&mpic>;
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reg = <90c00 80>;
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built-in;
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device_type = "cpm-pic";
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};
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scc@91a00 {
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SCC";
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device-id = <1>;
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reg = <91a00 20 88000 100>;
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clock-setup = <00ffffff 0>;
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rx-clock = <1>;
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tx-clock = <1>;
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current-speed = <1c200>;
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interrupts = <28 8>;
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interrupt-parent = <&cpmpic>;
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};
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scc@91a20 {
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SCC";
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device-id = <2>;
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reg = <91a20 20 88100 100>;
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clock-setup = <ff00ffff 90000>;
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rx-clock = <2>;
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tx-clock = <2>;
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current-speed = <1c200>;
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interrupts = <29 8>;
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interrupt-parent = <&cpmpic>;
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};
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fcc@91320 {
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device_type = "network";
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compatible = "fs_enet";
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model = "FCC";
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device-id = <2>;
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reg = <91320 20 88500 100 913a0 30>;
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mac-address = [ 00 00 0C 00 02 FD ];
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clock-setup = <ff00ffff 250000>;
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rx-clock = <15>;
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tx-clock = <16>;
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interrupts = <21 8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy2>;
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};
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fcc@91340 {
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device_type = "network";
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compatible = "fs_enet";
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model = "FCC";
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device-id = <3>;
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reg = <91340 20 88600 100 913d0 30>;
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mac-address = [ 00 00 0C 00 03 FD ];
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clock-setup = <ffff00ff 3700>;
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rx-clock = <17>;
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tx-clock = <18>;
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interrupts = <22 8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy3>;
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};
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};
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};
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};
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