02b7dd1244
Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
530 lines
13 KiB
ArmAsm
530 lines
13 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm1020.
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*
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* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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#include <asm/hardware.h>
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* The number of data cache segments.
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*/
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#define CACHE_DSEGMENTS 16
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/*
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* The number of lines in a cache segment.
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*/
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#define CACHE_DENTRIES 64
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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* cache line maintainence instructions.
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*/
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#define CACHE_DLIMIT 32768
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.text
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/*
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* cpu_arm1020_proc_init()
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*/
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ENTRY(cpu_arm1020_proc_init)
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mov pc, lr
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/*
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* cpu_arm1020_proc_fin()
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*/
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ENTRY(cpu_arm1020_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl arm1020_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_arm1020_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_arm1020_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_arm1020_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm1020_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/* ================================= CACHE ================================ */
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.align 5
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(arm1020_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm1020_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 5
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bcs 1b @ segments 15 to 0
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags for this space
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*/
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ENTRY(arm1020_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bhs __flush_whole_cache
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, ip, c7, c10, 4
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1020_coherent_kern_range)
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/* FALLTRHOUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1020_coherent_user_range)
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mov ip, #0
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcr p15, 0, ip, c7, c10, 4
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1:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#endif
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - page - page aligned address
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*/
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ENTRY(arm1020_flush_kern_dcache_page)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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ENTRY(arm1020_dma_inv_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, ip, c7, c10, 4
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, ip, c7, c10, 4
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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ENTRY(arm1020_dma_clean_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1020_dma_flush_range)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcr p15, 0, ip, c7, c10, 4
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(arm1020_cache_fns)
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.long arm1020_flush_kern_cache_all
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.long arm1020_flush_user_cache_all
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.long arm1020_flush_user_cache_range
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.long arm1020_coherent_kern_range
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.long arm1020_coherent_user_range
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.long arm1020_flush_kern_dcache_page
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.long arm1020_dma_inv_range
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.long arm1020_dma_clean_range
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.long arm1020_dma_flush_range
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.align 5
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ENTRY(cpu_arm1020_dcache_clean_area)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mov ip, #0
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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#endif
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_arm1020_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_arm1020_switch_mm)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r3, c7, c10, 4
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mov r1, #0xF @ 16 segments
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1: mov r3, #0x3F @ 64 entries
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2: mov ip, r3, LSL #26 @ shift up entry
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orr ip, ip, r1, LSL #5 @ shift in/up index
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mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
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mov ip, #0
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mcr p15, 0, ip, c7, c10, 4
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subs r3, r3, #1
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cmp r3, #0
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bge 2b @ entries 3F to 0
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subs r1, r1, #1
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cmp r1, #0
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bge 1b @ segments 15 to 0
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#endif
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mov r1, #0
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
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#endif
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, lr
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/*
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* cpu_arm1020_set_pte(ptep, pte)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_arm1020_set_pte)
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r1, #L_PTE_USER @ User?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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movne r2, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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eor r3, r1, #0x0a @ C & small page?
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tst r3, #0x0b
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biceq r2, r2, #4
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#endif
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str r2, [r0] @ hardware version
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mov r0, r0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 4
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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__INIT
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.type __arm1020_setup, #function
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__arm1020_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, arm1020_cr1_clear
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bic r0, r0, r5
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ldr r5, arm1020_cr1_set
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orr r0, r0, r5
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#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
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orr r0, r0, #0x4000 @ .R.. .... .... ....
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#endif
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mov pc, lr
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.size __arm1020_setup, . - __arm1020_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* .011 1001 ..11 0101
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*/
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.type arm1020_cr1_clear, #object
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.type arm1020_cr1_set, #object
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arm1020_cr1_clear:
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.word 0x593f
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arm1020_cr1_set:
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.word 0x3935
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm1020_processor_functions, #object
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arm1020_processor_functions:
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.word v4t_early_abort
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.word cpu_arm1020_proc_init
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.word cpu_arm1020_proc_fin
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.word cpu_arm1020_reset
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.word cpu_arm1020_do_idle
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.word cpu_arm1020_dcache_clean_area
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.word cpu_arm1020_switch_mm
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.word cpu_arm1020_set_pte
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.size arm1020_processor_functions, . - arm1020_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
|
|
cpu_arch_name:
|
|
.asciz "armv5t"
|
|
.size cpu_arch_name, . - cpu_arch_name
|
|
|
|
.type cpu_elf_name, #object
|
|
cpu_elf_name:
|
|
.asciz "v5"
|
|
.size cpu_elf_name, . - cpu_elf_name
|
|
|
|
.type cpu_arm1020_name, #object
|
|
cpu_arm1020_name:
|
|
.ascii "ARM1020"
|
|
#ifndef CONFIG_CPU_ICACHE_DISABLE
|
|
.ascii "i"
|
|
#endif
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
.ascii "d"
|
|
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
|
.ascii "(wt)"
|
|
#else
|
|
.ascii "(wb)"
|
|
#endif
|
|
#endif
|
|
#ifndef CONFIG_CPU_BPREDICT_DISABLE
|
|
.ascii "B"
|
|
#endif
|
|
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
|
.ascii "RR"
|
|
#endif
|
|
.ascii "\0"
|
|
.size cpu_arm1020_name, . - cpu_arm1020_name
|
|
|
|
.align
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
.type __arm1020_proc_info,#object
|
|
__arm1020_proc_info:
|
|
.long 0x4104a200 @ ARM 1020T (Architecture v5T)
|
|
.long 0xff0ffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __arm1020_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
|
|
.long cpu_arm1020_name
|
|
.long arm1020_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long v4wb_user_fns
|
|
.long arm1020_cache_fns
|
|
.size __arm1020_proc_info, . - __arm1020_proc_info
|