5a4a4ad851
Mark interrupts with no_action handler, cascade interrupts, low level interrupts (bus error, halt ..) with IRQF_NO_THREAD to exclude them from forced threading. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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* IRQ vector handles
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_gt641xx.h>
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#include <asm/gt64120.h>
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#include <irq.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
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int irq;
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if (pending & CAUSEF_IP2)
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gt641xx_irq_dispatch();
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else if (pending & CAUSEF_IP6) {
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irq = i8259_irq();
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if (irq < 0)
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spurious_interrupt();
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else
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do_IRQ(irq);
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} else if (pending & CAUSEF_IP3)
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do_IRQ(MIPS_CPU_IRQ_BASE + 3);
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else if (pending & CAUSEF_IP4)
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do_IRQ(MIPS_CPU_IRQ_BASE + 4);
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else if (pending & CAUSEF_IP5)
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do_IRQ(MIPS_CPU_IRQ_BASE + 5);
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else if (pending & CAUSEF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else
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spurious_interrupt();
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}
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static struct irqaction cascade = {
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.handler = no_action,
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.name = "cascade",
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.flags = IRQF_NO_THREAD,
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};
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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gt641xx_irq_init();
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init_i8259_irqs();
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setup_irq(GT641XX_CASCADE_IRQ, &cascade);
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setup_irq(I8259_CASCADE_IRQ, &cascade);
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}
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