570 lines
15 KiB
C
570 lines
15 KiB
C
/***********************************************************************
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* Based on arch/mips/ddb5xxx/ddb5477/setup.c
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*
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* Setup file for JMR3927.
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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***********************************************************************
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/irq.h>
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#include <linux/ioport.h>
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#include <linux/param.h> /* for HZ */
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#include <linux/delay.h>
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#include <linux/pm.h>
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#ifdef CONFIG_SERIAL_TXX9
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#endif
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#include <asm/addrspace.h>
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#include <asm/time.h>
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#include <asm/bcache.h>
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#include <asm/irq.h>
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#include <asm/reboot.h>
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#include <asm/gdb-stub.h>
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#include <asm/jmr3927/jmr3927.h>
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#include <asm/mipsregs.h>
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#include <asm/traps.h>
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extern void puts(unsigned char *cp);
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/* Tick Timer divider */
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#define JMR3927_TIMER_CCD 0 /* 1/2 */
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#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
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unsigned char led_state = 0xf;
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struct {
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struct resource ram0;
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struct resource ram1;
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struct resource pcimem;
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struct resource iob;
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struct resource ioc;
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struct resource pciio;
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struct resource jmy1394;
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struct resource rom1;
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struct resource rom0;
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struct resource sio0;
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struct resource sio1;
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} jmr3927_resources = {
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{
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.start = 0,
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.end = 0x01FFFFFF,
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.name = "RAM0",
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.flags = IORESOURCE_MEM
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}, {
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.start = 0x02000000,
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.end = 0x03FFFFFF,
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.name = "RAM1",
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.flags = IORESOURCE_MEM
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}, {
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.start = 0x08000000,
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.end = 0x07FFFFFF,
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.name = "PCIMEM",
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.flags = IORESOURCE_MEM
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}, {
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.start = 0x10000000,
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.end = 0x13FFFFFF,
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.name = "IOB"
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}, {
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.start = 0x14000000,
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.end = 0x14FFFFFF,
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.name = "IOC"
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}, {
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.start = 0x15000000,
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.end = 0x15FFFFFF,
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.name = "PCIIO"
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}, {
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.start = 0x1D000000,
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.end = 0x1D3FFFFF,
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.name = "JMY1394"
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}, {
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.start = 0x1E000000,
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.end = 0x1E3FFFFF,
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.name = "ROM1"
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}, {
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.start = 0x1FC00000,
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.end = 0x1FFFFFFF,
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.name = "ROM0"
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}, {
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.start = 0xFFFEF300,
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.end = 0xFFFEF3FF,
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.name = "SIO0"
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}, {
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.start = 0xFFFEF400,
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.end = 0xFFFEF4FF,
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.name = "SIO1"
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},
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};
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/* don't enable - see errata */
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int jmr3927_ccfg_toeon = 0;
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static inline void do_reset(void)
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{
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#ifdef CONFIG_TC35815
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extern void tc35815_killall(void);
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tc35815_killall();
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#endif
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#if 1 /* Resetting PCI bus */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
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jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
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mdelay(1);
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jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
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#endif
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jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
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}
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static void jmr3927_machine_restart(char *command)
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{
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local_irq_disable();
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puts("Rebooting...");
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do_reset();
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}
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static void jmr3927_machine_halt(void)
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{
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puts("JMR-TX3927 halted.\n");
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while (1);
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}
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static void jmr3927_machine_power_off(void)
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{
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puts("JMR-TX3927 halted. Please turn off the power.\n");
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while (1);
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}
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#define USE_RTC_DS1742
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#ifdef USE_RTC_DS1742
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extern void rtc_ds1742_init(unsigned long base);
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#endif
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static void __init jmr3927_time_init(void)
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{
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#ifdef USE_RTC_DS1742
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if (jmr3927_have_nvram()) {
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rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
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}
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#endif
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}
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unsigned long jmr3927_do_gettimeoffset(void);
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void __init plat_timer_setup(struct irqaction *irq)
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{
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do_gettimeoffset = jmr3927_do_gettimeoffset;
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jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
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jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
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jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
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jmr3927_tmrptr->tcr =
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TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
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setup_irq(JMR3927_IRQ_TICK, irq);
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}
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#define USECS_PER_JIFFY (1000000/HZ)
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unsigned long jmr3927_do_gettimeoffset(void)
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{
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unsigned long count;
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unsigned long res = 0;
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/* MUST read TRR before TISR. */
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count = jmr3927_tmrptr->trr;
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if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
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/* timer interrupt is pending. use Max value. */
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res = USECS_PER_JIFFY - 1;
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} else {
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/* convert to usec */
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/* res = count / (JMR3927_TIMER_CLK / 1000000); */
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res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY-1;
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}
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return res;
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}
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//#undef DO_WRITE_THROUGH
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#define DO_WRITE_THROUGH
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#define DO_ENABLE_CACHE
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extern char * __init prom_getcmdline(void);
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static void jmr3927_board_init(void);
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extern struct resource pci_io_resource;
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extern struct resource pci_mem_resource;
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void __init plat_mem_setup(void)
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{
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char *argptr;
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set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
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board_time_init = jmr3927_time_init;
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_machine_restart = jmr3927_machine_restart;
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_machine_halt = jmr3927_machine_halt;
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pm_power_off = jmr3927_machine_power_off;
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/*
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* IO/MEM resources.
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*/
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ioport_resource.start = pci_io_resource.start;
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ioport_resource.end = pci_io_resource.end;
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iomem_resource.start = 0;
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iomem_resource.end = 0xffffffff;
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/* Reboot on panic */
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panic_timeout = 180;
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{
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unsigned int conf;
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conf = read_c0_conf();
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}
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#if 1
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/* cache setup */
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{
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unsigned int conf;
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#ifdef DO_ENABLE_CACHE
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int mips_ic_disable = 0, mips_dc_disable = 0;
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#else
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int mips_ic_disable = 1, mips_dc_disable = 1;
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#endif
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#ifdef DO_WRITE_THROUGH
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int mips_config_cwfon = 0;
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int mips_config_wbon = 0;
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#else
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int mips_config_cwfon = 1;
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int mips_config_wbon = 1;
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#endif
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conf = read_c0_conf();
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conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
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conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
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conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
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conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
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conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
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write_c0_conf(conf);
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write_c0_cache(0);
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}
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#endif
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/* initialize board */
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jmr3927_board_init();
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argptr = prom_getcmdline();
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if ((argptr = strstr(argptr, "toeon")) != NULL) {
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jmr3927_ccfg_toeon = 1;
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}
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argptr = prom_getcmdline();
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if ((argptr = strstr(argptr, "ip=")) == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " ip=bootp");
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}
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#ifdef CONFIG_SERIAL_TXX9
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{
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extern int early_serial_txx9_setup(struct uart_port *port);
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int i;
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struct uart_port req;
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for(i = 0; i < 2; i++) {
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memset(&req, 0, sizeof(req));
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req.line = i;
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req.iotype = UPIO_MEM;
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req.membase = (char *)TX3927_SIO_REG(i);
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req.mapbase = TX3927_SIO_REG(i);
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req.irq = i == 0 ?
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JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
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if (i == 0)
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req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
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req.uartclk = JMR3927_IMCLK;
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early_serial_txx9_setup(&req);
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}
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}
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#ifdef CONFIG_SERIAL_TXX9_CONSOLE
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argptr = prom_getcmdline();
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if ((argptr = strstr(argptr, "console=")) == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " console=ttyS1,115200");
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}
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#endif
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#endif
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}
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static void tx3927_setup(void);
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#ifdef CONFIG_PCI
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unsigned long mips_pci_io_base;
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unsigned long mips_pci_io_size;
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unsigned long mips_pci_mem_base;
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unsigned long mips_pci_mem_size;
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/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
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unsigned long mips_pci_io_pciaddr = 0;
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#endif
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static void __init jmr3927_board_init(void)
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{
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char *argptr;
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#ifdef CONFIG_PCI
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mips_pci_io_base = JMR3927_PCIIO;
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mips_pci_io_size = JMR3927_PCIIO_SIZE;
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mips_pci_mem_base = JMR3927_PCIMEM;
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mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
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#endif
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tx3927_setup();
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if (jmr3927_have_isac()) {
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#ifdef CONFIG_FB_E1355
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argptr = prom_getcmdline();
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if ((argptr = strstr(argptr, "video=")) == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " video=e1355fb:crt16h");
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}
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#endif
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#ifdef CONFIG_BLK_DEV_IDE
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/* overrides PCI-IDE */
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#endif
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}
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/* SIO0 DTR on */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
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jmr3927_led_set(0);
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if (jmr3927_have_isac())
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jmr3927_io_led_set(0);
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printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
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jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
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jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
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jmr3927_dipsw1(), jmr3927_dipsw2(),
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jmr3927_dipsw3(), jmr3927_dipsw4());
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if (jmr3927_have_isac())
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printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
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jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
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jmr3927_io_dipsw());
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}
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void __init tx3927_setup(void)
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{
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int i;
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/* SDRAMC are configured by PROM */
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/* ROMC */
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tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
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tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
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tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
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tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
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/* CCFG */
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/* enable Timeout BusError */
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if (jmr3927_ccfg_toeon)
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
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/* clear BusErrorOnWrite flag */
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tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
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/* Disable PCI snoop */
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tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
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#ifdef DO_WRITE_THROUGH
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/* Enable PCI SNOOP - with write through only */
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
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#endif
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/* Pin selection */
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tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
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tx3927_ccfgptr->pcfg |=
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TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
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(TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
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printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
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tx3927_ccfgptr->crir,
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tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
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/* IRC */
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/* disable interrupt control */
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tx3927_ircptr->cer = 0;
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/* mask all IRC interrupts */
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tx3927_ircptr->imr = 0;
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for (i = 0; i < TX3927_NUM_IR / 2; i++) {
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tx3927_ircptr->ilr[i] = 0;
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}
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/* setup IRC interrupt mode (Low Active) */
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for (i = 0; i < TX3927_NUM_IR / 8; i++) {
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tx3927_ircptr->cr[i] = 0;
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}
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/* TMR */
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/* disable all timers */
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for (i = 0; i < TX3927_NR_TMR; i++) {
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tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
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tx3927_tmrptr(i)->tisr = 0;
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tx3927_tmrptr(i)->cpra = 0xffffffff;
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tx3927_tmrptr(i)->itmr = 0;
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tx3927_tmrptr(i)->ccdr = 0;
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tx3927_tmrptr(i)->pgmr = 0;
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}
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/* DMA */
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tx3927_dmaptr->mcr = 0;
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for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
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/* reset channel */
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tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
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tx3927_dmaptr->ch[i].ccr = 0;
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}
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/* enable DMA */
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#ifdef __BIG_ENDIAN
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tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
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#else
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tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
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#endif
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#ifdef CONFIG_PCI
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/* PCIC */
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printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
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tx3927_pcicptr->did, tx3927_pcicptr->vid,
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tx3927_pcicptr->rid);
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if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
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printk("External\n");
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/* XXX */
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} else {
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printk("Internal\n");
|
|
|
|
/* Reset PCI Bus */
|
|
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
|
|
udelay(100);
|
|
jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
|
|
JMR3927_IOC_RESET_ADDR);
|
|
udelay(100);
|
|
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
|
|
|
|
|
|
/* Disable External PCI Config. Access */
|
|
tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
|
|
#ifdef __BIG_ENDIAN
|
|
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
|
|
TX3927_PCIC_LBC_TIBSE |
|
|
TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
|
|
#endif
|
|
/* LB->PCI mappings */
|
|
tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
|
|
tx3927_pcicptr->ilbioma = mips_pci_io_base;
|
|
tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
|
|
tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
|
|
tx3927_pcicptr->ilbmma = mips_pci_mem_base;
|
|
tx3927_pcicptr->ipbmma = mips_pci_mem_base;
|
|
/* PCI->LB mappings */
|
|
tx3927_pcicptr->iobas = 0xffffffff;
|
|
tx3927_pcicptr->ioba = 0;
|
|
tx3927_pcicptr->tlbioma = 0;
|
|
tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
|
|
tx3927_pcicptr->mba = 0;
|
|
tx3927_pcicptr->tlbmma = 0;
|
|
#ifndef JMR3927_INIT_INDIRECT_PCI
|
|
/* Enable Direct mapping Address Space Decoder */
|
|
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
|
|
#endif
|
|
|
|
/* Clear All Local Bus Status */
|
|
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
|
|
/* Enable All Local Bus Interrupts */
|
|
tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
|
|
/* Clear All PCI Status Error */
|
|
tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
|
|
/* Enable All PCI Status Error Interrupts */
|
|
tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
|
|
|
|
/* PCIC Int => IRC IRQ10 */
|
|
tx3927_pcicptr->il = TX3927_IR_PCI;
|
|
#if 1
|
|
/* Target Control (per errata) */
|
|
tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
|
|
#endif
|
|
|
|
/* Enable Bus Arbiter */
|
|
#if 0
|
|
tx3927_pcicptr->req_trace = 0x73737373;
|
|
#endif
|
|
tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
|
|
|
|
tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY |
|
|
#if 1
|
|
PCI_COMMAND_IO |
|
|
#endif
|
|
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
|
}
|
|
#endif /* CONFIG_PCI */
|
|
|
|
/* PIO */
|
|
/* PIO[15:12] connected to LEDs */
|
|
tx3927_pioptr->dir = 0x0000f000;
|
|
tx3927_pioptr->maskcpu = 0;
|
|
tx3927_pioptr->maskext = 0;
|
|
{
|
|
unsigned int conf;
|
|
|
|
conf = read_c0_conf();
|
|
if (!(conf & TX39_CONF_ICE))
|
|
printk("TX3927 I-Cache disabled.\n");
|
|
if (!(conf & TX39_CONF_DCE))
|
|
printk("TX3927 D-Cache disabled.\n");
|
|
else if (!(conf & TX39_CONF_WBON))
|
|
printk("TX3927 D-Cache WriteThrough.\n");
|
|
else if (!(conf & TX39_CONF_CWFON))
|
|
printk("TX3927 D-Cache WriteBack.\n");
|
|
else
|
|
printk("TX3927 D-Cache WriteBack (CWF) .\n");
|
|
}
|
|
}
|