567bb8fd47
There is nothing in these routines that inherently depends on R0 use.
Given that these routines are inlined, it is rather easy to blow up the
compiler by exhausting the spill class when performing a 64-bit swab.
This presently manifests itself as the following:
CC fs/ocfs2/suballoc.o
fs/ocfs2/suballoc.c: In function 'ocfs2_reserve_suballoc_bits':
fs/ocfs2/suballoc.c:638: error: unrecognizable insn:
(insn 2793 1230 1231 103 arch/sh/include/asm/swab.h:33 (set (reg:HI 853)
(subreg:HI (reg:SI 149 macl) 2)) -1 (expr_list:REG_DEAD (reg:SI 149 macl)
(nil)))
fs/ocfs2/suballoc.c:638: internal compiler error: in extract_insn, at recog.c:1991
This patch switches over to using an arbitrarily assigned register instead.
While the same issue does not exist in the SH-5 case, there is likewise no harm
in having an alternate register used for the byterev/shari pair.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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|---|---|---|
| .. | ||
| asm | ||
| cpu-common/cpu | ||
| cpu-sh2/cpu | ||
| cpu-sh2a/cpu | ||
| cpu-sh3/cpu | ||
| cpu-sh4/cpu | ||
| cpu-sh5/cpu | ||
| mach-common/mach | ||
| mach-dreamcast/mach | ||
| mach-landisk/mach | ||
| mach-se/mach | ||
| mach-sh03/mach | ||