db97efffb8
(NOTE: This patch depends on upstream HMI handling patchset at https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-July/119731.html) The current HMI handling on napping cpus does not take care of endianess issue. On LE host kernel when we wake up from nap due to HMI interrupt we would checkstop while jumping into opal call. There is a similar issue in case of fast sleep wakeup where the code invokes opal_resync_tb opal call without handling LE issue. This patch fixes that as well. With this patch applied, HMIs handling on LE host kernel works fine. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
244 lines
5.3 KiB
ArmAsm
244 lines
5.3 KiB
ArmAsm
/*
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* This file contains the power_save function for Power7 CPUs.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/hw_irq.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/opal.h>
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#undef DEBUG
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/* Idle state entry routines */
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#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
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/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
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std r0,0(r1); \
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ptesync; \
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ld r0,0(r1); \
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1: cmp cr0,r0,r0; \
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bne 1b; \
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IDLE_INST; \
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b .
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.text
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/*
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* Pass requested state in r3:
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* 0 - nap
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* 1 - sleep
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*
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* To check IRQ_HAPPENED in r4
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* 0 - don't check
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* 1 - check
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*/
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_GLOBAL(power7_powersave_common)
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/* Use r3 to pass state nap/sleep/winkle */
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/* NAP is a state loss, we create a regs frame on the
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* stack, fill it up with the state we care about and
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* stick a pointer to it in PACAR1. We really only
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* need to save PC, some CR bits and the NV GPRs,
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* but for now an interrupt frame will do.
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*/
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mflr r0
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std r0,16(r1)
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stdu r1,-INT_FRAME_SIZE(r1)
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std r0,_LINK(r1)
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std r0,_NIP(r1)
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#ifndef CONFIG_SMP
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/* Make sure FPU, VSX etc... are flushed as we may lose
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* state when going to nap mode
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*/
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bl discard_lazy_cpu_state
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#endif /* CONFIG_SMP */
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/* Hard disable interrupts */
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mfmsr r9
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rldicl r9,r9,48,1
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rotldi r9,r9,16
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mtmsrd r9,1 /* hard-disable interrupts */
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/* Check if something happened while soft-disabled */
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lbz r0,PACAIRQHAPPENED(r13)
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cmpwi cr0,r0,0
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beq 1f
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cmpwi cr0,r4,0
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beq 1f
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addi r1,r1,INT_FRAME_SIZE
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ld r0,16(r1)
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mtlr r0
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blr
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1: /* We mark irqs hard disabled as this is the state we'll
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* be in when returning and we need to tell arch_local_irq_restore()
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* about it
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*/
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li r0,PACA_IRQ_HARD_DIS
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stb r0,PACAIRQHAPPENED(r13)
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/* We haven't lost state ... yet */
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li r0,0
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stb r0,PACA_NAPSTATELOST(r13)
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/* Continue saving state */
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SAVE_GPR(2, r1)
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SAVE_NVGPRS(r1)
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mfcr r4
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std r4,_CCR(r1)
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std r9,_MSR(r1)
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std r1,PACAR1(r13)
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_GLOBAL(power7_enter_nap_mode)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/* Tell KVM we're napping */
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li r4,KVM_HWTHREAD_IN_NAP
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stb r4,HSTATE_HWTHREAD_STATE(r13)
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#endif
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cmpwi cr0,r3,1
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beq 2f
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IDLE_STATE_ENTER_SEQ(PPC_NAP)
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/* No return */
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2: IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
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/* No return */
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_GLOBAL(power7_idle)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDRBASE(r3,powersave_nap)
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lwz r4,ADDROFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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li r3, 1
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/* fall through */
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_GLOBAL(power7_nap)
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mr r4,r3
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li r3,0
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b power7_powersave_common
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/* No return */
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_GLOBAL(power7_sleep)
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li r3,1
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li r4,1
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b power7_powersave_common
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/* No return */
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/*
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* Make opal call in realmode. This is a generic function to be called
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* from realmode from reset vector. It handles endianess.
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*
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* r13 - paca pointer
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* r1 - stack pointer
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* r3 - opal token
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*/
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opal_call_realmode:
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mflr r12
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std r12,_LINK(r1)
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ld r2,PACATOC(r13)
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/* Set opal return address */
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LOAD_REG_ADDR(r0,return_from_opal_call)
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mtlr r0
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/* Handle endian-ness */
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li r0,MSR_LE
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mfmsr r12
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andc r12,r12,r0
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mtspr SPRN_HSRR1,r12
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mr r0,r3 /* Move opal token to r0 */
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LOAD_REG_ADDR(r11,opal)
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ld r12,8(r11)
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ld r2,0(r11)
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mtspr SPRN_HSRR0,r12
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hrfid
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return_from_opal_call:
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FIXUP_ENDIAN
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ld r0,_LINK(r1)
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mtlr r0
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blr
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#define CHECK_HMI_INTERRUPT \
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mfspr r0,SPRN_SRR1; \
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BEGIN_FTR_SECTION_NESTED(66); \
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rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
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FTR_SECTION_ELSE_NESTED(66); \
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rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
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ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
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cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
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bne 20f; \
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/* Invoke opal call to handle hmi */ \
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ld r2,PACATOC(r13); \
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ld r1,PACAR1(r13); \
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std r3,ORIG_GPR3(r1); /* Save original r3 */ \
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li r3,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
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bl opal_call_realmode; \
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ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
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20: nop;
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_GLOBAL(power7_wakeup_tb_loss)
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ld r2,PACATOC(r13);
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ld r1,PACAR1(r13)
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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/* Time base re-sync */
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li r3,OPAL_RESYNC_TIMEBASE
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bl opal_call_realmode;
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/* TODO: Check r3 for failure */
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REST_NVGPRS(r1)
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REST_GPR(2, r1)
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ld r3,_CCR(r1)
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ld r4,_MSR(r1)
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ld r5,_NIP(r1)
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addi r1,r1,INT_FRAME_SIZE
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mtcr r3
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mfspr r3,SPRN_SRR1 /* Return SRR1 */
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mtspr SPRN_SRR1,r4
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mtspr SPRN_SRR0,r5
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rfid
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_GLOBAL(power7_wakeup_loss)
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ld r1,PACAR1(r13)
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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REST_NVGPRS(r1)
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REST_GPR(2, r1)
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ld r3,_CCR(r1)
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ld r4,_MSR(r1)
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ld r5,_NIP(r1)
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addi r1,r1,INT_FRAME_SIZE
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mtcr r3
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mtspr SPRN_SRR1,r4
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mtspr SPRN_SRR0,r5
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rfid
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_GLOBAL(power7_wakeup_noloss)
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lbz r0,PACA_NAPSTATELOST(r13)
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cmpwi r0,0
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bne power7_wakeup_loss
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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ld r1,PACAR1(r13)
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ld r4,_MSR(r1)
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ld r5,_NIP(r1)
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addi r1,r1,INT_FRAME_SIZE
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mtspr SPRN_SRR1,r4
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mtspr SPRN_SRR0,r5
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rfid
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