1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
1076 lines
25 KiB
C
1076 lines
25 KiB
C
/*
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* linux/arch/arm/mach-omap/clock.c
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*
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* Copyright (C) 2004 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/semaphore.h>
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#include <asm/hardware/clock.h>
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#include <asm/arch/board.h>
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#include <asm/arch/usb.h>
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#include "clock.h"
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static LIST_HEAD(clocks);
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static DECLARE_MUTEX(clocks_sem);
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static DEFINE_SPINLOCK(clockfw_lock);
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static void propagate_rate(struct clk * clk);
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/* External clock (MCLK & BCLK) functions */
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static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
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static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
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static void init_ext_clk(struct clk * clk);
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/* MPU virtual clock functions */
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static int select_table_rate(struct clk * clk, unsigned long rate);
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static long round_to_table_rate(struct clk * clk, unsigned long rate);
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void clk_setdpll(__u16, __u16);
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struct mpu_rate rate_table[] = {
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/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
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* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
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*/
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#if defined(CONFIG_OMAP_ARM_216MHZ)
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{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
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#endif
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#if defined(CONFIG_OMAP_ARM_195MHZ)
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{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
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#endif
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#if defined(CONFIG_OMAP_ARM_192MHZ)
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{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
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{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
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{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
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{ 48000000, 12000000, 192000000, 0x0ccf, 0x2810 }, /* 4/4/4/4/8/8 */
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{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
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#endif
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#if defined(CONFIG_OMAP_ARM_182MHZ)
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{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
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#endif
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#if defined(CONFIG_OMAP_ARM_168MHZ)
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{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
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#endif
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#if defined(CONFIG_OMAP_ARM_150MHZ)
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{ 150000000, 12000000, 150000000, 0x150a, 0x2cb0 }, /* 0/0/1/1/2/2 */
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#endif
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#if defined(CONFIG_OMAP_ARM_120MHZ)
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{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
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#endif
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#if defined(CONFIG_OMAP_ARM_96MHZ)
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{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
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#endif
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#if defined(CONFIG_OMAP_ARM_60MHZ)
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{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
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#endif
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#if defined(CONFIG_OMAP_ARM_30MHZ)
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{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
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#endif
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{ 0, 0, 0, 0, 0 },
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};
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static void ckctl_recalc(struct clk * clk)
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{
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int dsor;
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/* Calculate divisor encoded as 2-bit exponent */
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dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
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if (unlikely(clk->rate == clk->parent->rate / dsor))
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return; /* No change, quick exit */
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clk->rate = clk->parent->rate / dsor;
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if (unlikely(clk->flags & RATE_PROPAGATES))
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propagate_rate(clk);
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}
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static void followparent_recalc(struct clk * clk)
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{
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clk->rate = clk->parent->rate;
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}
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static void watchdog_recalc(struct clk * clk)
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{
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clk->rate = clk->parent->rate / 14;
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}
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static struct clk ck_ref = {
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.name = "ck_ref",
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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ALWAYS_ENABLED,
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};
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static struct clk ck_dpll1 = {
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.name = "ck_dpll1",
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_PROPAGATES | ALWAYS_ENABLED,
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};
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static struct clk ck_dpll1out = {
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.name = "ck_dpll1out",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_CKOUT_ARM,
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.recalc = &followparent_recalc,
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};
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static struct clk arm_ck = {
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.name = "arm_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
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.rate_offset = CKCTL_ARMDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk armper_ck = {
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.name = "armper_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_PERCK,
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk arm_gpio_ck = {
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.name = "arm_gpio_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_GPIOCK,
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.recalc = &followparent_recalc,
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};
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static struct clk armxor_ck = {
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.name = "armxor_ck",
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_XORPCK,
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.recalc = &followparent_recalc,
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};
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static struct clk armtim_ck = {
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.name = "armtim_ck",
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_TIMCK,
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.recalc = &followparent_recalc,
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};
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static struct clk armwdt_ck = {
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.name = "armwdt_ck",
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_WDTCK,
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.recalc = &watchdog_recalc,
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};
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static struct clk arminth_ck16xx = {
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.name = "arminth_ck",
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.parent = &arm_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.recalc = &followparent_recalc,
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/* Note: On 16xx the frequency can be divided by 2 by programming
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* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
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*
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* 1510 version is in TC clocks.
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*/
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};
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static struct clk dsp_ck = {
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.name = "dsp_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL,
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.enable_reg = ARM_CKCTL,
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.enable_bit = EN_DSPCK,
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.rate_offset = CKCTL_DSPDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk dspmmu_ck = {
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.name = "dspmmu_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | ALWAYS_ENABLED,
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.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk tc_ck = {
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.name = "tc_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
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RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
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.rate_offset = CKCTL_TCDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk arminth_ck1510 = {
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.name = "arminth_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP1510,
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.recalc = &followparent_recalc,
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/* Note: On 1510 the frequency follows TC_CK
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*
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* 16xx version is in MPU clocks.
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*/
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};
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static struct clk tipb_ck = {
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.name = "tibp_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP1510,
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.recalc = &followparent_recalc,
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};
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static struct clk l3_ocpi_ck = {
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.name = "l3_ocpi_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT3,
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.enable_bit = EN_OCPI_CK,
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.recalc = &followparent_recalc,
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};
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static struct clk tc1_ck = {
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.name = "tc1_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT3,
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.enable_bit = EN_TC1_CK,
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.recalc = &followparent_recalc,
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};
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static struct clk tc2_ck = {
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.name = "tc2_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT3,
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.enable_bit = EN_TC2_CK,
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.recalc = &followparent_recalc,
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};
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static struct clk dma_ck = {
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.name = "dma_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.recalc = &followparent_recalc,
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};
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static struct clk dma_lcdfree_ck = {
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.name = "dma_lcdfree_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.recalc = &followparent_recalc,
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};
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static struct clk api_ck = {
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.name = "api_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_APICK,
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.recalc = &followparent_recalc,
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};
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static struct clk lb_ck = {
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.name = "lb_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP1510,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_LBCK,
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.recalc = &followparent_recalc,
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};
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static struct clk rhea1_ck = {
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.name = "rhea1_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.recalc = &followparent_recalc,
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};
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static struct clk rhea2_ck = {
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.name = "rhea2_ck",
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.parent = &tc_ck,
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.flags = CLOCK_IN_OMAP16XX,
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.recalc = &followparent_recalc,
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};
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static struct clk lcd_ck = {
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.name = "lcd_ck",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
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RATE_CKCTL,
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.enable_reg = ARM_IDLECT2,
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.enable_bit = EN_LCDCK,
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.rate_offset = CKCTL_LCDDIV_OFFSET,
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.recalc = &ckctl_recalc,
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};
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static struct clk uart1_ck = {
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.name = "uart1_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = 29,
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/* (Only on 1510)
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* The "enable bit" actually chooses between 48MHz and 12MHz.
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*/
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};
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static struct clk uart2_ck = {
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.name = "uart2_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = 30,
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/* (for both 1510 and 16xx)
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* The "enable bit" actually chooses between 48MHz and 12MHz/32kHz.
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*/
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};
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static struct clk uart3_ck = {
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.name = "uart3_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = 31,
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/* (Only on 1510)
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* The "enable bit" actually chooses between 48MHz and 12MHz.
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*/
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};
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static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
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.name = "usb_clko",
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/* Direct from ULPD, no parent */
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.rate = 6000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = ULPD_CLOCK_CTRL,
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.enable_bit = USB_MCLK_EN_BIT,
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};
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static struct clk usb_hhc_ck1510 = {
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.name = "usb_hhc_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
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.flags = CLOCK_IN_OMAP1510 |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = USB_HOST_HHC_UHOST_EN,
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};
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static struct clk usb_hhc_ck16xx = {
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.name = "usb_hhc_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
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.flags = CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
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.enable_bit = 8 /* UHOST_EN */,
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};
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static struct clk mclk_1510 = {
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.name = "mclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
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};
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static struct clk mclk_16xx = {
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.name = "mclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = COM_CLK_DIV_CTRL_SEL,
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.enable_bit = COM_ULPD_PLL_CLK_REQ,
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.set_rate = &set_ext_clk_rate,
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.round_rate = &round_ext_clk_rate,
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.init = &init_ext_clk,
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};
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static struct clk bclk_1510 = {
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.name = "bclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
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};
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static struct clk bclk_16xx = {
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.name = "bclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.flags = CLOCK_IN_OMAP16XX,
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.enable_reg = SWD_CLK_DIV_CTRL_SEL,
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.enable_bit = SWD_ULPD_PLL_CLK_REQ,
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.set_rate = &set_ext_clk_rate,
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.round_rate = &round_ext_clk_rate,
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.init = &init_ext_clk,
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};
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static struct clk mmc1_ck = {
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.name = "mmc1_ck",
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/* Functional clock is direct from ULPD, interface clock is ARMPER */
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.parent = &armper_ck,
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = 23,
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};
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static struct clk mmc2_ck = {
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.name = "mmc2_ck",
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/* Functional clock is direct from ULPD, interface clock is ARMPER */
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.parent = &armper_ck,
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP16XX |
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RATE_FIXED | ENABLE_REG_32BIT,
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.enable_reg = MOD_CONF_CTRL_0,
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.enable_bit = 20,
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};
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static struct clk virtual_ck_mpu = {
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.name = "mpu",
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
|
|
VIRTUAL_CLOCK | ALWAYS_ENABLED,
|
|
.parent = &arm_ck, /* Is smarter alias for */
|
|
.recalc = &followparent_recalc,
|
|
.set_rate = &select_table_rate,
|
|
.round_rate = &round_to_table_rate,
|
|
};
|
|
|
|
|
|
static struct clk * onchip_clks[] = {
|
|
/* non-ULPD clocks */
|
|
&ck_ref,
|
|
&ck_dpll1,
|
|
/* CK_GEN1 clocks */
|
|
&ck_dpll1out,
|
|
&arm_ck,
|
|
&armper_ck,
|
|
&arm_gpio_ck,
|
|
&armxor_ck,
|
|
&armtim_ck,
|
|
&armwdt_ck,
|
|
&arminth_ck1510, &arminth_ck16xx,
|
|
/* CK_GEN2 clocks */
|
|
&dsp_ck,
|
|
&dspmmu_ck,
|
|
/* CK_GEN3 clocks */
|
|
&tc_ck,
|
|
&tipb_ck,
|
|
&l3_ocpi_ck,
|
|
&tc1_ck,
|
|
&tc2_ck,
|
|
&dma_ck,
|
|
&dma_lcdfree_ck,
|
|
&api_ck,
|
|
&lb_ck,
|
|
&rhea1_ck,
|
|
&rhea2_ck,
|
|
&lcd_ck,
|
|
/* ULPD clocks */
|
|
&uart1_ck,
|
|
&uart2_ck,
|
|
&uart3_ck,
|
|
&usb_clko,
|
|
&usb_hhc_ck1510, &usb_hhc_ck16xx,
|
|
&mclk_1510, &mclk_16xx,
|
|
&bclk_1510, &bclk_16xx,
|
|
&mmc1_ck,
|
|
&mmc2_ck,
|
|
/* Virtual clocks */
|
|
&virtual_ck_mpu,
|
|
};
|
|
|
|
struct clk *clk_get(struct device *dev, const char *id)
|
|
{
|
|
struct clk *p, *clk = ERR_PTR(-ENOENT);
|
|
|
|
down(&clocks_sem);
|
|
list_for_each_entry(p, &clocks, node) {
|
|
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
|
|
clk = p;
|
|
break;
|
|
}
|
|
}
|
|
up(&clocks_sem);
|
|
|
|
return clk;
|
|
}
|
|
EXPORT_SYMBOL(clk_get);
|
|
|
|
|
|
void clk_put(struct clk *clk)
|
|
{
|
|
if (clk && !IS_ERR(clk))
|
|
module_put(clk->owner);
|
|
}
|
|
EXPORT_SYMBOL(clk_put);
|
|
|
|
|
|
int __clk_enable(struct clk *clk)
|
|
{
|
|
__u16 regval16;
|
|
__u32 regval32;
|
|
|
|
if (clk->flags & ALWAYS_ENABLED)
|
|
return 0;
|
|
|
|
if (unlikely(clk->enable_reg == 0)) {
|
|
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
|
|
clk->name);
|
|
return 0;
|
|
}
|
|
|
|
if (clk->flags & ENABLE_REG_32BIT) {
|
|
regval32 = omap_readl(clk->enable_reg);
|
|
regval32 |= (1 << clk->enable_bit);
|
|
omap_writel(regval32, clk->enable_reg);
|
|
} else {
|
|
regval16 = omap_readw(clk->enable_reg);
|
|
regval16 |= (1 << clk->enable_bit);
|
|
omap_writew(regval16, clk->enable_reg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void __clk_disable(struct clk *clk)
|
|
{
|
|
__u16 regval16;
|
|
__u32 regval32;
|
|
|
|
if (clk->enable_reg == 0)
|
|
return;
|
|
|
|
if (clk->flags & ENABLE_REG_32BIT) {
|
|
regval32 = omap_readl(clk->enable_reg);
|
|
regval32 &= ~(1 << clk->enable_bit);
|
|
omap_writel(regval32, clk->enable_reg);
|
|
} else {
|
|
regval16 = omap_readw(clk->enable_reg);
|
|
regval16 &= ~(1 << clk->enable_bit);
|
|
omap_writew(regval16, clk->enable_reg);
|
|
}
|
|
}
|
|
|
|
|
|
void __clk_unuse(struct clk *clk)
|
|
{
|
|
if (clk->usecount > 0 && !(--clk->usecount)) {
|
|
__clk_disable(clk);
|
|
if (likely(clk->parent))
|
|
__clk_unuse(clk->parent);
|
|
}
|
|
}
|
|
|
|
|
|
int __clk_use(struct clk *clk)
|
|
{
|
|
int ret = 0;
|
|
if (clk->usecount++ == 0) {
|
|
if (likely(clk->parent))
|
|
ret = __clk_use(clk->parent);
|
|
|
|
if (unlikely(ret != 0)) {
|
|
clk->usecount--;
|
|
return ret;
|
|
}
|
|
|
|
ret = __clk_enable(clk);
|
|
|
|
if (unlikely(ret != 0) && clk->parent) {
|
|
__clk_unuse(clk->parent);
|
|
clk->usecount--;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
ret = __clk_enable(clk);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_enable);
|
|
|
|
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
__clk_disable(clk);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
}
|
|
EXPORT_SYMBOL(clk_disable);
|
|
|
|
|
|
int clk_use(struct clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
ret = __clk_use(clk);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_use);
|
|
|
|
|
|
void clk_unuse(struct clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
__clk_unuse(clk);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
}
|
|
EXPORT_SYMBOL(clk_unuse);
|
|
|
|
|
|
int clk_get_usecount(struct clk *clk)
|
|
{
|
|
return clk->usecount;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_usecount);
|
|
|
|
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
return clk->rate;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_rate);
|
|
|
|
|
|
static __u16 verify_ckctl_value(__u16 newval)
|
|
{
|
|
/* This function checks for following limitations set
|
|
* by the hardware (all conditions must be true):
|
|
* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
|
|
* ARM_CK >= TC_CK
|
|
* DSP_CK >= TC_CK
|
|
* DSPMMU_CK >= TC_CK
|
|
*
|
|
* In addition following rules are enforced:
|
|
* LCD_CK <= TC_CK
|
|
* ARMPER_CK <= TC_CK
|
|
*
|
|
* However, maximum frequencies are not checked for!
|
|
*/
|
|
__u8 per_exp;
|
|
__u8 lcd_exp;
|
|
__u8 arm_exp;
|
|
__u8 dsp_exp;
|
|
__u8 tc_exp;
|
|
__u8 dspmmu_exp;
|
|
|
|
per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
|
|
lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
|
|
arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
|
|
dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
|
|
tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
|
|
dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
|
|
|
|
if (dspmmu_exp < dsp_exp)
|
|
dspmmu_exp = dsp_exp;
|
|
if (dspmmu_exp > dsp_exp+1)
|
|
dspmmu_exp = dsp_exp+1;
|
|
if (tc_exp < arm_exp)
|
|
tc_exp = arm_exp;
|
|
if (tc_exp < dspmmu_exp)
|
|
tc_exp = dspmmu_exp;
|
|
if (tc_exp > lcd_exp)
|
|
lcd_exp = tc_exp;
|
|
if (tc_exp > per_exp)
|
|
per_exp = tc_exp;
|
|
|
|
newval &= 0xf000;
|
|
newval |= per_exp << CKCTL_PERDIV_OFFSET;
|
|
newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
|
|
newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
|
|
newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
|
|
newval |= tc_exp << CKCTL_TCDIV_OFFSET;
|
|
newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
|
|
|
|
return newval;
|
|
}
|
|
|
|
|
|
static int calc_dsor_exp(struct clk *clk, unsigned long rate)
|
|
{
|
|
/* Note: If target frequency is too low, this function will return 4,
|
|
* which is invalid value. Caller must check for this value and act
|
|
* accordingly.
|
|
*
|
|
* Note: This function does not check for following limitations set
|
|
* by the hardware (all conditions must be true):
|
|
* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
|
|
* ARM_CK >= TC_CK
|
|
* DSP_CK >= TC_CK
|
|
* DSPMMU_CK >= TC_CK
|
|
*/
|
|
unsigned long realrate;
|
|
struct clk * parent;
|
|
unsigned dsor_exp;
|
|
|
|
if (unlikely(!(clk->flags & RATE_CKCTL)))
|
|
return -EINVAL;
|
|
|
|
parent = clk->parent;
|
|
if (unlikely(parent == 0))
|
|
return -EIO;
|
|
|
|
realrate = parent->rate;
|
|
for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
|
|
if (realrate <= rate)
|
|
break;
|
|
|
|
realrate /= 2;
|
|
}
|
|
|
|
return dsor_exp;
|
|
}
|
|
|
|
long clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int dsor_exp;
|
|
|
|
if (clk->flags & RATE_FIXED)
|
|
return clk->rate;
|
|
|
|
if (clk->flags & RATE_CKCTL) {
|
|
dsor_exp = calc_dsor_exp(clk, rate);
|
|
if (dsor_exp < 0)
|
|
return dsor_exp;
|
|
if (dsor_exp > 3)
|
|
dsor_exp = 3;
|
|
return clk->parent->rate / (1 << dsor_exp);
|
|
}
|
|
|
|
if(clk->round_rate != 0)
|
|
return clk->round_rate(clk, rate);
|
|
|
|
return clk->rate;
|
|
}
|
|
EXPORT_SYMBOL(clk_round_rate);
|
|
|
|
|
|
static void propagate_rate(struct clk * clk)
|
|
{
|
|
struct clk ** clkp;
|
|
|
|
for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
|
|
if (likely((*clkp)->parent != clk)) continue;
|
|
if (likely((*clkp)->recalc))
|
|
(*clkp)->recalc(*clkp);
|
|
}
|
|
}
|
|
|
|
|
|
static int select_table_rate(struct clk * clk, unsigned long rate)
|
|
{
|
|
/* Find the highest supported frequency <= rate and switch to it */
|
|
struct mpu_rate * ptr;
|
|
|
|
if (clk != &virtual_ck_mpu)
|
|
return -EINVAL;
|
|
|
|
for (ptr = rate_table; ptr->rate; ptr++) {
|
|
if (ptr->xtal != ck_ref.rate)
|
|
continue;
|
|
|
|
/* DPLL1 cannot be reprogrammed without risking system crash */
|
|
if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
|
|
continue;
|
|
|
|
/* Can check only after xtal frequency check */
|
|
if (ptr->rate <= rate)
|
|
break;
|
|
}
|
|
|
|
if (!ptr->rate)
|
|
return -EINVAL;
|
|
|
|
if (unlikely(ck_dpll1.rate == 0)) {
|
|
omap_writew(ptr->dpllctl_val, DPLL_CTL);
|
|
ck_dpll1.rate = ptr->pll_rate;
|
|
}
|
|
omap_writew(ptr->ckctl_val, ARM_CKCTL);
|
|
propagate_rate(&ck_dpll1);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static long round_to_table_rate(struct clk * clk, unsigned long rate)
|
|
{
|
|
/* Find the highest supported frequency <= rate */
|
|
struct mpu_rate * ptr;
|
|
long highest_rate;
|
|
|
|
if (clk != &virtual_ck_mpu)
|
|
return -EINVAL;
|
|
|
|
highest_rate = -EINVAL;
|
|
|
|
for (ptr = rate_table; ptr->rate; ptr++) {
|
|
if (ptr->xtal != ck_ref.rate)
|
|
continue;
|
|
|
|
highest_rate = ptr->rate;
|
|
|
|
/* Can check only after xtal frequency check */
|
|
if (ptr->rate <= rate)
|
|
break;
|
|
}
|
|
|
|
return highest_rate;
|
|
}
|
|
|
|
|
|
int clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
int dsor_exp;
|
|
__u16 regval;
|
|
unsigned long flags;
|
|
|
|
if (clk->flags & RATE_CKCTL) {
|
|
dsor_exp = calc_dsor_exp(clk, rate);
|
|
if (dsor_exp > 3)
|
|
dsor_exp = -EINVAL;
|
|
if (dsor_exp < 0)
|
|
return dsor_exp;
|
|
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
regval = omap_readw(ARM_CKCTL);
|
|
regval &= ~(3 << clk->rate_offset);
|
|
regval |= dsor_exp << clk->rate_offset;
|
|
regval = verify_ckctl_value(regval);
|
|
omap_writew(regval, ARM_CKCTL);
|
|
clk->rate = clk->parent->rate / (1 << dsor_exp);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
ret = 0;
|
|
} else if(clk->set_rate != 0) {
|
|
spin_lock_irqsave(&clockfw_lock, flags);
|
|
ret = clk->set_rate(clk, rate);
|
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
|
}
|
|
|
|
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
|
|
propagate_rate(clk);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_set_rate);
|
|
|
|
|
|
static unsigned calc_ext_dsor(unsigned long rate)
|
|
{
|
|
unsigned dsor;
|
|
|
|
/* MCLK and BCLK divisor selection is not linear:
|
|
* freq = 96MHz / dsor
|
|
*
|
|
* RATIO_SEL range: dsor <-> RATIO_SEL
|
|
* 0..6: (RATIO_SEL+2) <-> (dsor-2)
|
|
* 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
|
|
* Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
|
|
* can not be used.
|
|
*/
|
|
for (dsor = 2; dsor < 96; ++dsor) {
|
|
if ((dsor & 1) && dsor > 8)
|
|
continue;
|
|
if (rate >= 96000000 / dsor)
|
|
break;
|
|
}
|
|
return dsor;
|
|
}
|
|
|
|
|
|
static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
|
|
{
|
|
unsigned dsor;
|
|
__u16 ratio_bits;
|
|
|
|
dsor = calc_ext_dsor(rate);
|
|
clk->rate = 96000000 / dsor;
|
|
if (dsor > 8)
|
|
ratio_bits = ((dsor - 8) / 2 + 6) << 2;
|
|
else
|
|
ratio_bits = (dsor - 2) << 2;
|
|
|
|
ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
|
|
omap_writew(ratio_bits, clk->enable_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static long round_ext_clk_rate(struct clk * clk, unsigned long rate)
|
|
{
|
|
return 96000000 / calc_ext_dsor(rate);
|
|
}
|
|
|
|
|
|
static void init_ext_clk(struct clk * clk)
|
|
{
|
|
unsigned dsor;
|
|
__u16 ratio_bits;
|
|
|
|
/* Determine current rate and ensure clock is based on 96MHz APLL */
|
|
ratio_bits = omap_readw(clk->enable_reg) & ~1;
|
|
omap_writew(ratio_bits, clk->enable_reg);
|
|
|
|
ratio_bits = (ratio_bits & 0xfc) >> 2;
|
|
if (ratio_bits > 6)
|
|
dsor = (ratio_bits - 6) * 2 + 8;
|
|
else
|
|
dsor = ratio_bits + 2;
|
|
|
|
clk-> rate = 96000000 / dsor;
|
|
}
|
|
|
|
|
|
int clk_register(struct clk *clk)
|
|
{
|
|
down(&clocks_sem);
|
|
list_add(&clk->node, &clocks);
|
|
if (clk->init)
|
|
clk->init(clk);
|
|
up(&clocks_sem);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(clk_register);
|
|
|
|
void clk_unregister(struct clk *clk)
|
|
{
|
|
down(&clocks_sem);
|
|
list_del(&clk->node);
|
|
up(&clocks_sem);
|
|
}
|
|
EXPORT_SYMBOL(clk_unregister);
|
|
|
|
|
|
|
|
int __init clk_init(void)
|
|
{
|
|
struct clk ** clkp;
|
|
const struct omap_clock_config *info;
|
|
int crystal_type = 0; /* Default 12 MHz */
|
|
|
|
for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
|
|
if (info != NULL) {
|
|
if (!cpu_is_omap1510())
|
|
crystal_type = info->system_clock_type;
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_OMAP730)
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|
ck_ref.rate = 13000000;
|
|
#elif defined(CONFIG_ARCH_OMAP16XX)
|
|
if (crystal_type == 2)
|
|
ck_ref.rate = 19200000;
|
|
#endif
|
|
|
|
/* We want to be in syncronous scalable mode */
|
|
omap_writew(0x1000, ARM_SYSST);
|
|
|
|
/* Find the highest supported frequency and enable it */
|
|
if (select_table_rate(&virtual_ck_mpu, ~0)) {
|
|
printk(KERN_ERR "System frequencies not set. Check your config.\n");
|
|
/* Guess sane values (60MHz) */
|
|
omap_writew(0x2290, DPLL_CTL);
|
|
omap_writew(0x1005, ARM_CKCTL);
|
|
ck_dpll1.rate = 60000000;
|
|
propagate_rate(&ck_dpll1);
|
|
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n",
|
|
ck_ref.rate, ck_dpll1.rate, arm_ck.rate);
|
|
}
|
|
|
|
/* Cache rates for clocks connected to ck_ref (not dpll1) */
|
|
propagate_rate(&ck_ref);
|
|
|
|
#ifdef CONFIG_MACH_OMAP_PERSEUS2
|
|
/* Select slicer output as OMAP input clock */
|
|
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
|
|
#endif
|
|
|
|
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
|
|
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
|
|
|
|
/* Put DSP/MPUI into reset until needed */
|
|
omap_writew(0, ARM_RSTCT1);
|
|
omap_writew(1, ARM_RSTCT2);
|
|
omap_writew(0x400, ARM_IDLECT1);
|
|
|
|
/*
|
|
* According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
|
|
* of the ARM_IDLECT2 register must be set to zero. The power-on
|
|
* default value of this bit is one.
|
|
*/
|
|
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
|
|
|
|
/*
|
|
* Only enable those clocks we will need, let the drivers
|
|
* enable other clocks as necessary
|
|
*/
|
|
clk_use(&armper_ck);
|
|
clk_use(&armxor_ck);
|
|
clk_use(&armtim_ck);
|
|
|
|
if (cpu_is_omap1510())
|
|
clk_enable(&arm_gpio_ck);
|
|
|
|
return 0;
|
|
}
|