a9686e0d20
I'd missed some of these out, breaking the av7110 tuning. I then checked for more and added them in where necessary. They may not actually be necessary in all these locations, but if not, they'll simply have no effect. Add small delay to stv0299 pll gate control to fix tuning problems. Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
125 lines
3.7 KiB
C
125 lines
3.7 KiB
C
/*
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* bsbe1.h - ALPS BSBE1 tuner support (moved from av7110.c)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*
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*
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* the project's page is at http://www.linuxtv.org
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*/
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#ifndef BSBE1_H
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#define BSBE1_H
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static u8 alps_bsbe1_inittab[] = {
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0x01, 0x15,
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0x02, 0x30,
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0x03, 0x00,
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0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
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0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
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0x06, 0x40, /* DAC not used, set to high impendance mode */
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0x07, 0x00, /* DAC LSB */
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0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
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0x09, 0x00, /* FIFO */
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0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
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0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
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0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
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0x10, 0x3f, // AGC2 0x3d
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0x11, 0x84,
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0x12, 0xb9,
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0x15, 0xc9, // lock detector threshold
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0x16, 0x00,
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0x17, 0x00,
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0x18, 0x00,
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0x19, 0x00,
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0x1a, 0x00,
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0x1f, 0x50,
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0x20, 0x00,
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0x21, 0x00,
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0x22, 0x00,
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0x23, 0x00,
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0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
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0x29, 0x1e, // 1/2 threshold
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0x2a, 0x14, // 2/3 threshold
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0x2b, 0x0f, // 3/4 threshold
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0x2c, 0x09, // 5/6 threshold
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0x2d, 0x05, // 7/8 threshold
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0x2e, 0x01,
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0x31, 0x1f, // test all FECs
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0x32, 0x19, // viterbi and synchro search
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0x33, 0xfc, // rs control
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0x34, 0x93, // error control
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0x0f, 0x92,
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0xff, 0xff
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};
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static int alps_bsbe1_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
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{
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u8 aclk = 0;
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u8 bclk = 0;
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if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
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else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
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else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
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else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
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else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
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else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
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stv0299_writereg(fe, 0x13, aclk);
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stv0299_writereg(fe, 0x14, bclk);
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stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
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stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
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stv0299_writereg(fe, 0x21, (ratio ) & 0xf0);
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return 0;
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}
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static int alps_bsbe1_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend_parameters *params)
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{
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int ret;
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u8 data[4];
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u32 div;
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struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
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struct i2c_adapter *i2c = fe->tuner_priv;
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if ((params->frequency < 950000) || (params->frequency > 2150000))
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return -EINVAL;
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div = (params->frequency + (125 - 1)) / 125; // round correctly
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data[0] = (div >> 8) & 0x7f;
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data[1] = div & 0xff;
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data[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
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data[3] = (params->frequency > 1530000) ? 0xE0 : 0xE4;
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if (fe->ops->i2c_gate_ctrl)
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fe->ops->i2c_gate_ctrl(fe, 1);
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ret = i2c_transfer(i2c, &msg, 1);
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return (ret != 1) ? -EIO : 0;
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}
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static struct stv0299_config alps_bsbe1_config = {
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.demod_address = 0x68,
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.inittab = alps_bsbe1_inittab,
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.mclk = 88000000UL,
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.invert = 1,
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.skip_reinit = 0,
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.min_delay_ms = 100,
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.set_symbol_rate = alps_bsbe1_set_symbol_rate,
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};
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#endif
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