24f1e32c60
This patch rebase the implementation of the breakpoints API on top of
perf events instances.
Each breakpoints are now perf events that handle the
register scheduling, thread/cpu attachment, etc..
The new layering is now made as follows:
ptrace kgdb ftrace perf syscall
\ | / /
\ | / /
/
Core breakpoint API /
/
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Breakpoints perf events
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Breakpoints PMU ---- Debug Register constraints handling
(Part of core breakpoint API)
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Hardware debug registers
Reasons of this rewrite:
- Use the centralized/optimized pmu registers scheduling,
implying an easier arch integration
- More powerful register handling: perf attributes (pinned/flexible
events, exclusive/non-exclusive, tunable period, etc...)
Impact:
- New perf ABI: the hardware breakpoints counters
- Ptrace breakpoints setting remains tricky and still needs some per
thread breakpoints references.
Todo (in the order):
- Support breakpoints perf counter events for perf tools (ie: implement
perf_bpcounter_event())
- Support from perf tools
Changes in v2:
- Follow the perf "event " rename
- The ptrace regression have been fixed (ptrace breakpoint perf events
weren't released when a task ended)
- Drop the struct hw_breakpoint and store generic fields in
perf_event_attr.
- Separate core and arch specific headers, drop
asm-generic/hw_breakpoint.h and create linux/hw_breakpoint.h
- Use new generic len/type for breakpoint
- Handle off case: when breakpoints api is not supported by an arch
Changes in v3:
- Fix broken CONFIG_KVM, we need to propagate the breakpoint api
changes to kvm when we exit the guest and restore the bp registers
to the host.
Changes in v4:
- Drop the hw_breakpoint_restore() stub as it is only used by KVM
- EXPORT_SYMBOL_GPL hw_breakpoint_restore() as KVM can be built as a
module
- Restore the breakpoints unconditionally on kvm guest exit:
TIF_DEBUG_THREAD doesn't anymore cover every cases of running
breakpoints and vcpu->arch.switch_db_regs might not always be
set when the guest used debug registers.
(Waiting for a reliable optimization)
Changes in v5:
- Split-up the asm-generic/hw-breakpoint.h moving to
linux/hw_breakpoint.h into a separate patch
- Optimize the breakpoints restoring while switching from kvm guest
to host. We only want to restore the state if we have active
breakpoints to the host, otherwise we don't care about messed-up
address registers.
- Add asm/hw_breakpoint.h to Kbuild
- Fix bad breakpoint type in trace_selftest.c
Changes in v6:
- Fix wrong header inclusion in trace.h (triggered a build
error with CONFIG_FTRACE_SELFTEST
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Prasad <prasad@linux.vnet.ibm.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jan Kiszka <jan.kiszka@web.de>
Cc: Jiri Slaby <jirislaby@gmail.com>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Masami Hiramatsu <mhiramat@redhat.com>
Cc: Paul Mundt <lethal@linux-sh.org>
231 lines
5.5 KiB
C
231 lines
5.5 KiB
C
/*
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* Suspend support specific for i386/x86-64.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/suspend.h>
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#include <linux/smp.h>
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#include <asm/pgtable.h>
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#include <asm/proto.h>
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#include <asm/mtrr.h>
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#include <asm/page.h>
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#include <asm/mce.h>
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#include <asm/xcr.h>
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#include <asm/suspend.h>
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#include <asm/debugreg.h>
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#ifdef CONFIG_X86_32
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static struct saved_context saved_context;
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unsigned long saved_context_ebx;
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unsigned long saved_context_esp, saved_context_ebp;
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unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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#else
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/* CONFIG_X86_64 */
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struct saved_context saved_context;
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#endif
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/**
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* __save_processor_state - save CPU registers before creating a
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* hibernation image and before restoring the memory state from it
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* @ctxt - structure to store the registers contents in
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*
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* NOTE: If there is a CPU register the modification of which by the
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* boot kernel (ie. the kernel used for loading the hibernation image)
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* might affect the operations of the restored target kernel (ie. the one
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* saved in the hibernation image), then its contents must be saved by this
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* function. In other words, if kernel A is hibernated and different
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* kernel B is used for loading the hibernation image into memory, the
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* kernel A's __save_processor_state() function must save all registers
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* needed by kernel A, so that it can operate correctly after the resume
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* regardless of what kernel B does in the meantime.
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*/
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static void __save_processor_state(struct saved_context *ctxt)
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{
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#ifdef CONFIG_X86_32
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mtrr_save_fixed_ranges(NULL);
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#endif
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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#ifdef CONFIG_X86_32
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store_gdt(&ctxt->gdt);
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store_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
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store_idt((struct desc_ptr *)&ctxt->idt_limit);
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#endif
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store_tr(ctxt->tr);
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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savesegment(es, ctxt->es);
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savesegment(fs, ctxt->fs);
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savesegment(gs, ctxt->gs);
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savesegment(ss, ctxt->ss);
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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rdmsrl(MSR_FS_BASE, ctxt->fs_base);
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rdmsrl(MSR_GS_BASE, ctxt->gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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mtrr_save_fixed_ranges(NULL);
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rdmsrl(MSR_EFER, ctxt->efer);
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#endif
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/*
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* control registers
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*/
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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#ifdef CONFIG_X86_32
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ctxt->cr4 = read_cr4_safe();
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#else
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/* CONFIG_X86_64 */
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ctxt->cr4 = read_cr4();
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ctxt->cr8 = read_cr8();
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#endif
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}
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/* Needed by apm.c */
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(save_processor_state);
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#endif
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary.
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*/
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kernel_fpu_end();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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#ifdef CONFIG_X86_64
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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#endif
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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* @ctxt - structure to load the registers contents from
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*/
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static void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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#ifdef CONFIG_X86_32
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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#ifdef CONFIG_X86_32
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load_gdt(&ctxt->gdt);
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load_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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loadsegment(ss, ctxt->ss);
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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#endif
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/*
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* restore XCR0 for xsave capable cpu's.
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*/
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if (cpu_has_xsave)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
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fix_processor_context();
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do_fpu_end();
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mtrr_bp_restore();
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}
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/* Needed by apm.c */
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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#endif
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