5296b56d1b
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
10 lines
371 B
Makefile
10 lines
371 B
Makefile
obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
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obj-$(CONFIG_NET_DMA) += iovlock.o
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obj-$(CONFIG_DMATEST) += dmatest.o
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obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
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ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
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obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_MV_XOR) += mv_xor.o
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obj-$(CONFIG_DW_DMAC) += dw_dmac.o
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obj-$(CONFIG_MX3_IPU) += ipu/
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