61a6976bf1
This takes a bit of a sledgehammer to the horribly CPU subtype ifdef-ridden header and abstracts all of the different register layouts in to distinct types which in turn can be overriden on a per-port basis, or permitted to default to the map matching the port type at probe time. In the process this ultimately fixes up inumerable bugs with mismatches on various CPU types (particularly the legacy ones that were obviously broken years ago and no one noticed) and provides a more tightly coupled and consolidated platform for extending and implementing generic features. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
133 lines
2.9 KiB
C
133 lines
2.9 KiB
C
#ifndef __LINUX_SERIAL_SCI_H
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#define __LINUX_SERIAL_SCI_H
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#include <linux/serial_core.h>
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#include <linux/sh_dma.h>
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/*
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* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
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*/
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#define SCIx_NOT_SUPPORTED (-1)
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enum {
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SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
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SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
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SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
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SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
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SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
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};
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#define SCSCR_TIE (1 << 7)
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#define SCSCR_RIE (1 << 6)
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#define SCSCR_TE (1 << 5)
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#define SCSCR_RE (1 << 4)
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#define SCSCR_REIE (1 << 3) /* not supported by all parts */
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#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
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#define SCSCR_CKE1 (1 << 1)
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#define SCSCR_CKE0 (1 << 0)
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/* SCxSR SCI */
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#define SCI_TDRE 0x80
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#define SCI_RDRF 0x40
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#define SCI_ORER 0x20
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#define SCI_FER 0x10
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#define SCI_PER 0x08
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#define SCI_TEND 0x04
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080
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#define SCIF_TEND 0x0040
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#define SCIF_TDFE 0x0020
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#define SCIF_BRK 0x0010
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#define SCIF_FER 0x0008
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#define SCIF_PER 0x0004
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#define SCIF_RDF 0x0002
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#define SCIF_DR 0x0001
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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SCIx_RXI_IRQ,
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SCIx_TXI_IRQ,
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SCIx_BRI_IRQ,
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SCIx_NR_IRQS,
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};
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enum {
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SCIx_PROBE_REGTYPE,
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SCIx_SCI_REGTYPE,
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SCIx_IRDA_REGTYPE,
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SCIx_SCIFA_REGTYPE,
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SCIx_SCIFB_REGTYPE,
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SCIx_SH3_SCIF_REGTYPE,
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SCIx_SH4_SCIF_REGTYPE,
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SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
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SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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SCIx_SH7705_SCIF_REGTYPE,
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SCIx_NR_REGTYPES,
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};
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#define SCIx_IRQ_MUXED(irq) \
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{ \
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[SCIx_ERI_IRQ] = (irq), \
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[SCIx_RXI_IRQ] = (irq), \
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[SCIx_TXI_IRQ] = (irq), \
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[SCIx_BRI_IRQ] = (irq), \
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}
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, SCBRR, SCSCR, SCxSR,
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SCFCR, SCFDR, SCxTDR, SCxRDR,
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SCLSR, SCTFDR, SCRFDR, SCSPTR,
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SCIx_NR_REGS,
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};
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struct device;
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struct plat_sci_port_ops {
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void (*init_pins)(struct uart_port *, unsigned int cflag);
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};
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/*
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* Platform device specific platform_data struct
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*/
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struct plat_sci_port {
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unsigned long mapbase; /* resource base */
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unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
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unsigned int type; /* SCI / SCIF / IRDA */
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upf_t flags; /* UPF_* flags */
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unsigned int scbrr_algo_id; /* SCBRR calculation algo */
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unsigned int scscr; /* SCSCR initialization */
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/*
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* Platform overrides if necessary, defaults otherwise.
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*/
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int overrun_bit;
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unsigned int error_mask;
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int port_reg;
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unsigned char regshift;
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unsigned char regtype;
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struct plat_sci_port_ops *ops;
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struct device *dma_dev;
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unsigned int dma_slave_tx;
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unsigned int dma_slave_rx;
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};
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#endif /* __LINUX_SERIAL_SCI_H */
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