David S. Miller 24f287e412 [SPARC64]: Implement atomic backoff. ... When the cpu count is high and contention hits an atomic object, the processors can synchronize such that some cpus continually get knocked out and cannot complete the atomic update. So implement an exponential backoff when SMP. Signed-off-by: David S. Miller <davem@davemloft.net>		2007-10-17 16:24:55 -07:00
..
atomic.S	[SPARC64]: Implement atomic backoff.	2007-10-17 16:24:55 -07:00
bitops.S	[SPARC64]: Implement atomic backoff.	2007-10-17 16:24:55 -07:00
bzero.S	[SPARC64]: __bzero_noasi --> __clear_user	2006-03-20 01:13:28 -08:00
checksum.S	[SPARC64]: Fix missing fold at end of checksums.	2006-06-04 21:32:01 -07:00
clear_page.S	[SPARC64]: Deal with PTE layout differences in SUN4V.	2006-03-20 01:12:25 -08:00
copy_in_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
copy_page.S	[SPARC64]: Deal with PTE layout differences in SUN4V.	2006-03-20 01:12:25 -08:00
csum_copy.S	[SPARC64]: Fix missing fold at end of checksums.	2006-06-04 21:32:01 -07:00
csum_copy_from_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
csum_copy_to_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
GENbzero.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
GENcopy_from_user.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
GENcopy_to_user.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
GENmemcpy.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
GENpage.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
GENpatch.S	[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.	2007-08-08 17:33:45 -07:00
iomap.c
ipcsum.S
Makefile	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
mcount.S	Remove obsolete #include <linux/config.h>	2006-06-30 19:25:36 +02:00
memcmp.S
memmove.S
memscan.S
NG2copy_from_user.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NG2copy_to_user.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NG2memcpy.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NG2page.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NG2patch.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NGbzero.S	[SPARC64]: store-init needs trailing membar.	2007-03-19 13:27:33 -07:00
NGcopy_from_user.S	[SPARC64]: Fix missing load-twin usage in Niagara-1 memcpy.	2007-10-02 01:03:09 -07:00
NGcopy_to_user.S	[SPARC64]: Fix missing load-twin usage in Niagara-1 memcpy.	2007-10-02 01:03:09 -07:00
NGmemcpy.S	[SPARC64]: Don't use in/local regs for ldx/stx data in N1 memcpy.	2007-10-02 16:17:17 -07:00
NGpage.S	[SPARC64]: Niagara-2 optimized copies.	2007-08-16 01:47:25 -07:00
NGpatch.S	[SPARC64]: Fix branch signedness bug in all code patching.	2006-03-20 01:12:29 -08:00
PeeCeeI.c
rwsem.S
strlen.S
strlen_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
strncmp.S
strncpy_from_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
U1copy_from_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
U1copy_to_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
U1memcpy.S
U3copy_from_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
U3copy_to_user.S	[SPARC64]: Mark __ex_table section correctly.	2006-03-04 23:23:56 -08:00
U3memcpy.S
U3patch.S	[SPARC64]: Fix branch signedness bug in all code patching.	2006-03-20 01:12:29 -08:00
user_fixup.c
VISsave.S
xor.S	[SPARC64]: Fix register usage in xor_raid_4().	2007-10-13 21:53:14 -07:00